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CDCR83DBQR Datasheet(PDF) 7 Page - Texas Instruments |
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CDCR83DBQR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 16 page CDCR83 DIRECT RAMBUS CLOCK GENERATOR SCAS632B − APRIL 2001 − REVISED OCTOBER 2005 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tc(out) Clock output cycle time 2.5 3.75 ns Total cycle jitter over 1, 2, Infinite and 267 MHz 80 t(jitter) Total cycle jitter over 1, 2, 3, 4, 5, or 6 clock cycles Infinite and stopped phase 300 MHz See Figure 3 70 ps t(jitter) 3, 4, 5, or 6 clock cycles stopped phase alignment 356 MHz See Figure 3 60 ps alignment 400 MHz 50 t(phase) Phase detector phase error for distributed loop Static phase error} −100 100 ps t(phase, SSC) PLL output phase error when tracking SSC Dynamic phase error} −100 100 ps t(DC) Output duty cycle over 10,000 cycles See Figure 4 45% 55% Infinite and 267 MHz 80 t(DC, err) Output cycle-to-cycle Infinite and stopped phase 300 MHz See Figure 5 70 ps t(DC, err) Output cycle-to-cycle duty cycle error stopped phase alignment 356 MHz See Figure 5 60 ps duty cycle error alignment 400 MHz 50 tr, tf Output rise and fall times (measured at 20%−80% of output voltage) See Figure 7 160 400 ps ∆t Difference between rise and fall times on a single device (20%−80%) |tf − tr| See Figure 7 100 ps † All typical values are at VDD = 3.3 V, TA = 25°C. ‡ Assured by design state transition latency specifications PARAMETER FROM TO TEST CONDITIONS MIN TYP† MAX UNIT t(powerup) Delay time, PWRDNB ↑ to CLK/CLKB output settled (excluding t(DISTLOCK)) Powerdown Normal See Figure 8 3 ms t(powerup) Delay time, PWRDNB ↑ to internal PLL and clock are on and settled Powerdown Normal 3 ms t(VDDpowerup) Delay time, power up to CLK/CLKB output settled VDD Normal See Figure 8 3 ms t(VDDpowerup) Delay time, power up to internal PLL and clock are on and settled VDD Normal 3 ms t(MULT) MULT0 and MULT1 change to CLK/CLKB output resettled (excluding t(DISTLOCK)) Normal Normal See Figure 9 1 ms t(CLKON) STOPB ↑ to CLK/CLKB glitch-free clock edges CLK Stop Normal See Figure 10 10 ns t(CLKSETL) STOPB ↑ to CLK/CLKB output settled to within 50 ps of the phase before STOPB was disabled CLK Stop Normal See Figure 10 20 cycles t(CLKOFF) STOPB ↓ to CLK/CLKB output disabled Normal CLK Stop See Figure 10 5 ns † All typical values are at VDD = 3.3 V, TA = 25°C. |
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