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CDCM6208V2GRGZT Datasheet(PDF) 51 Page - Texas Instruments |
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CDCM6208V2GRGZT Datasheet(HTML) 51 Page - Texas Instruments |
51 / 88 page 51 CDCM6208V2G www.ti.com SNAS682 – MARCH 2016 Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter. Table 28. Register 18 BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 15 RESERVED This bit must be set to 0 14 RESERVED This bit must be set to 0 13 RESERVED This bit must be set to 0 12:10 PRE_DIV_CH7[2:0] Output Channel 7 Output channel 7 fractional divider's 3-b pre-divider setting (this pre- divider is bypassed if Q18.9 = 0) 000 → Divide by 2 001 → Divide by 3 111 → Divide by 1 All other combinations reserved 9 EN_FRACDIV_CH7 Output channel 7 fractional divider enable: 0 → Disable, 1 → Enable 8 LVCMOS_SLEW_CH7 Output channel 7 LVCMOS output slew: 0 → Normal, 1 → Slow 7 EN_LVCMOS_N_CH7 Output channel 7 negative-side LVCMOS enable: 0 → Disable, 1 → Enable (Negative side can only be enabled if positive side is enabled) 6 EN_LVCMOS_P_CH7 Output channel 7 positive-side LVCMOS enable: 0 → Disable, 1 → Enable 5 RESERVED This bit must be set to 0 4:3 SEL_DRVR_CH7[2:0] Output channel 7 type selection:00 or 01 → LVDS, 10 → LVCMOS, 11 → HCSL 2:1 EN_CH7[1:0] Output channel 7 enable: 00 → Disable, 01 → Enable, 10 → Drive static low, 11 → Drive static high 0 SUPPLY_CH7 (1) Output channel 7 Supply Voltage Selection: 0 → 1.8 V, 1 → 2.5/3.3 V Table 29. Register 19 BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 15 RESERVED This bit must be set to 0 14 RESERVED This bit must be set to 0 13 RESERVED This bit must be set to 0 12 RESERVED This bit must be set to 0 11:4 OUTDIV7[7:0] Output Channel 7 Output channel 7 8-b integer divider setting (Divider value is register value +1) 3:0 FRACDIV7[19:16] Output channel 7 20-b fractional divider setting, bits 19-16 Table 30. Register 20 BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 15:0 FRACDIV7[15:0] Output Channel 7 Output channel 7 20-b fractional divider setting, bits 15-0 |
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