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CDCM7005-SP Datasheet(PDF) 40 Page - Texas Instruments |
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CDCM7005-SP Datasheet(HTML) 40 Page - Texas Instruments |
40 / 49 page S0082-01 VCXO Low-PassFilter CDCM7005 245.76MHz Gain=21.3kHz/V PECL_OUT_B PRI_REF VCXO_IN YnA YnB VCXO_IN CTRL_DATA CTRL_LE CTRL_CLK V_CTRL CP_OUT PLL_LOCK STATUS_REF STATUS_VCXO PECL_OUT SPI V OC V OC R 130W R 82W R 150W R 50W R 82W R 150W R 50W R2 160W R 130W R1 4.7kW C2 100nF C1 22 F m 10nF 10nF C3 100nF Measurement Equipment PhaseNoiseReferenceCircuit(SeetheEVM) 40 CDCM7005-SP SGLS390G – JULY 2009 – REVISED NOVEMBER 2015 www.ti.com Product Folder Links: CDCM7005-SP Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated 10.2 Typical Application Figure 27. Typical Application Diagram With Passive Loop Filter 10.2.1 Design Requirements Before PLL design starts, design targets and constraints should be specified. Design targets include: output frequency, output phase noise or output jitter over certain band, maximum lock time or maximum dynamic frequency deviation during settling. Design constraints might include: input frequency, specific VCO/VCXO device, certain type of filter (for example, passive) Most probably VCO/VCXO is determined based on the noise requirements, or frequency plan needs. Input frequency is typically given by application or system needs. Power or noise requirement might dictate certain type of filter. |
Similar Part No. - CDCM7005-SP_16 |
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Similar Description - CDCM7005-SP_16 |
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