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CDCM6208V2GRGZR Datasheet(PDF) 34 Page - Texas Instruments |
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CDCM6208V2GRGZR Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 88 page  34 CDCM6208V2G SNAS682 – MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Table 5. CDCM6208V2G Loop Filter Recommendation for Pin Mode (continued) Use Case PRI_REF SEC_REF f(PFD) (MHz) ICP (mA) Recommended External LPF Components C1 / R2 / C2 Internal LPF Components Freq (MHz) Type Freq (MHz) Type R3 (Ω) C3 (pF) 10 0x18 25-V2G 125 CML 25 LVCMOS MAN- SEC 6.25 4m 22pF / 860Ω / 22nF 100 242.5 10 0x19 26-V2G 35.328 LVCMOS 35.328 Crystal MAN- SEC 35.328 2.5m 22pF / 400Ω / 22nF 100 242.5 10 0x1A 27-V2G 35.328 LVCMOS 35.328 Crystal MAN- SEC 35.328 2.5m 22pF / 400Ω / 22nF 100 242.5 10 0x1B 28-V2G 0.192 LVCMOS 0.192 LVCMOS MAN- SEC 0.192 3.5m 100pF / 2.67kΩ / 6.8nF 100 242.5 10 0x1C 29-V2G 25 LVCMOS 25 Crystal MAN- SEC 25 2.5m 100pF / 470Ω / 22nF 100 242.5 10 0x1D 30-V2G 50 LVCMOS 50 Crystal MAN- SEC 25 2.5m 100pF / 470Ω / 22nF 100 242.5 10 0x1E 31-V2G 50 LVCMOS 50 Crystal MAN- SEC 25 2.5m 100pF / 470Ω / 22nF 100 242.5 10 0x1F 32-V2G 50 LVCMOS 50 Crystal MAN- SEC 25 2.5m 100pF / 470Ω / 22nF 100 242.5 (1) The reverse logic between the register Q21.2 and the external output signal on STATUS0 or STATUS1. 10.4.3 Status Pins Definition The device vitals such as input signal quality, smart mux input selection, and PLL lock can be monitored by reading device registers or at the status pins STATUS1, and STATUS0. Register 3[12:7] allows for customization of which vitals are mapped to these two pins. Table 6 lists the three events that can be mapped to each status pin and which can also be read in the register space. Table 6. CDCM6208V2G Status Pin Definition List STATUS SIGNAL NAME SIGNAL TYPE SIGNAL NAME REGISTER BIT NO. DESCRIPTION SEL_REF LVCMOS STATUS0, 1 Reg 3.12 Reg 3.9 Indicates Reference Selected for PLL: 0 → Primary input selected to drive PLL 1 → Secondary input selected to drive PLL LOS_REF LVCMOS STATUS0, 1 Reg 3.11 Reg 3.8 Loss of selected reference input observed at active input: 0 → Reference input present 1 → Loss of reference input Important Note 1: For LOS_REF to operate properly, the secondary input SEC_IN must be enabled. Set register Q4.5=1. If register Q4.5 is set to zero, LOS_REF will output a static high signal regardless of the actual input signal status on PRI_IN. PLL_UNLOCK LVCMOS STATUS0, 1 Reg 3.10 Reg 3.7 Indicates unlock status for PLL (digital): PLL locked → Q21.02 = 0 and VSTATUS0/1= VIH PLL unlocked → Q21.2 = 1 and VSTATUS0/1= VILSee note (1) Note 2: I f the smartmux is enabled and both reference clocks stall, the STATUSx output signal will 98% of the time indicate the LOS condition with a static high signal. However, in 2% of the cases, the LOS detection engine erroneously stalls at a state where the STATUSx output PLL lock indicator will signalize high for 511 out of every 512 PFD clock cycles. |
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