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DS125BR820NJYT Datasheet(PDF) 1 Page - Texas Instruments |
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DS125BR820NJYT Datasheet(HTML) 1 Page - Texas Instruments |
1 / 62 page VDD INA_0+ INA_0- AD0 AD1 AD2 AD3 ENSMB SCL (2) READ_EN ALL_DONE SDA (2) OUTA_0+ OUTA_0- . . . . . . GND . . . (1) Schematic requires different connections for SMBus Master Mode and Pin Mode (2) SMBus signals need to be pulled up elsewhere in the system. (3) Schematic requires different connections for 3.3 V mode . . . VDD To system SMBus Address straps (pull-up or pull-down) 1F 0.1F (5x) SMBus Slave Mode (1) 2.5V . . . INA_3+ INA_3- OUTA_3+ OUTA_3- SMBus Slave Mode (1) VDD_SEL VIN 2.5 V Mode (3) INB_0+ INB_0- OUTB_0+ OUTB_0- . . . . . . . . . . . . . . . INB_3+ INB_3- OUTB_3+ OUTB_3- 10F Line Card DS125BR820 2x40G DS125BR820 ASIC FPGA 2x40G DS125BR820 8x10G DS125BR820 8x10G Stacked QSFP+ 40GbE Copper CR4 or 40GbE SR4/LR4 Optical Stacked QSFP+ 1xQSFP+ to 4xSFP+ Breakout Product Folder Sample & Buy Technical Documents Tools & Software Support & Community DS125BR820 SNLS491B – JULY 2014 – REVISED FEBRUARY 2015 DS125BR820 Low-Power 12.5 Gbps 8-Channel Linear Repeater 1 Features 3 Description The DS125BR820 is an extremely low-power high- 1 • Low 70 mW/Channel (Typ) Power Consumption, performance repeater/redriver designed to support with Option to Power Down Unused Channels eight channels carrying high speed interface up to • Seamless Link Training Support 12.5 Gbps, such as 40G-CR4, 40G-KR4, SAS/SATA, • Enables Host ASIC to Meet Front-Port Eye Mask and PCIe. The receiver's continuous time linear equalizer (CTLE) provides high frequency boost that Requirements over Longer Reach is programmable from 3 to 10 dB at 6 GHz (12 Gbps) • Advanced Configurable Signal Conditioning I/O followed by a linear output driver. The CTLE receiver – Receive CTLE up to 10 dB at 6 GHz is capable of opening an input eye that is completely – Linear Output Driver closed due to inter symbol interference (ISI) induced by interconnect medium such as board traces or twin – Variable Output Voltage Range up to 1200 axial-copper cables. The programmable equalization mVp-p maximizes the flexibility of physical placement within • Programmable via Pin Selection, EEPROM, or the interconnect channel and improves overall SMBus Interface channel performance. • Single Supply Voltage: 2.5 V or 3.3 V When operating in 40G-CR4/KR4, SAS/SATA, and • −40°C to 85°C Operating Temperature Range PCIe applications, the DS125BR820 preserves transmit signal characteristics, thereby allowing the • Flow-Thru Layout in 10 mm × 5.5 mm 54-Pin host controller and the end point to negotiate transmit Leadless WQFN Package equalizer coefficients. This transparency in the link training protocol facilitates system level 2 Applications interoperability and minimizes latency. • Front-Port 40G-CR4/SR4/LR4 Link Extension The programmable settings can be applied easily via • Backplane 40G-KR4 Link Extension pin control, software (SMBus or I2C), or direct loading • SAS/SATA/PCIe Link Extension from an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on • Other Proprietary High Speed Interfaces up to power up, thereby eliminating the need for an 12.5 Gbps external microprocessor or software driver. Simplified Functional Block Diagram Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DS125BR820 WQFN (54) 10 mm × 5.5 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Block Diagram 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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