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DS125BR401ANJYR Datasheet(PDF) 4 Page - Texas Instruments |
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DS125BR401ANJYR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 52 page  DS125BR401A SNLS466A – SEPTEMBER 2013 – REVISED MARCH 2014 www.ti.com Terminal Functions(1) TERMINAL TERMINAL NAME I/O, TYPE TERMINAL DESCRIPTION NUMBER DIFFERENTIAL HIGH SPEED I/O INB_0+, INB_0- , 45, 44, 43, 42 I Inverting and non-inverting CML differential inputs to the equalizer. On- INB_1+, INB_1-, 40, 39, 38, 37 chip 50 Ω termination resistor connects INB_n+ to VDD and INB_n- to INB_2+, INB_2-, VDD when enabled. INB_3+, INB_3- AC coupling required on high-speed I/O OUTB_0+, OUTB_0-, 1, 2, 3, 4 O Inverting and non-inverting 50 Ω driver outputs with de-emphasis. OUTB_1+, OUTB_1-, 5, 6, 7, 8 Compatible with AC coupled CML inputs. OUTB_2+, OUTB_2-, AC coupling required on high-speed I/O OUTB_3+, OUTB_3- INA_0+, INA_0- , 10, 11, 12, 13 I Inverting and non-inverting CML differential inputs to the equalizer. On- INA_1+, INA_1-, 15, 16, 17, 18 chip 50 Ω termination resistor connects INA_n+ to VDD and INA_n- to INA_2+, INA_2-, VDD when enabled. INA_3+, INA_3- AC coupling required on high-speed I/O OUTA_0+, OUTA_0-, 35, 34, 33, 32 O Inverting and non-inverting 50 Ω driver outputs. Compatible with AC OUTA_1+, OUTA_1-, 31, 30, 29, 28 coupled CML inputs. OUTA_2+, OUTA_2-, AC coupling required on high-speed I/O OUTA_3+, OUTA_3- CONTROL TERMINALS — SHARED (LVCMOS) ENSMB 48 I, LVCMOS System Management Bus (SMBus) enable Terminal Tie 1k Ω to VDD = Register Access SMBus Slave mode FLOAT = Read External EEPROM (Master SMBUS Mode) Tie 1k Ω to GND = Terminal Mode ENSMB = 1 (SMBus MODE) SCL 50 I, LVCMOS, ENSMB Master or Slave mode O, OPEN Drain SMBus clock input Terminal is enabled (slave mode). Clock output when loading EEPROM configuration (master mode). SDA 49 I, LVCMOS, ENSMB Master or Slave mode O, OPEN Drain The SMBus bidirectional SDA Terminal is enabled. Data input or open drain (pull-down only) output. AD0-AD3 54, 53, 47, 46 I, LVCMOS ENSMB Master or Slave mode SMBus Slave Address Inputs. In SMBus mode, these Terminals are the user set SMBus slave address inputs. READ_EN 26 I, LVCMOS When using an External EEPROM, a logic low on this terminal starts the load from the external EEPROM ENSMB = 0 (TERMINAL MODE) EQA0, EQA1 20, 19 I, 4-LEVEL, EQA[1:0] and EQB[1:0] control the level of equalization of the A/B EQB0, EQB1 46, 47 LVCMOS directions. The Terminals are defined as EQx[1:0] only when ENSMB is de-asserted (low). Each of the 4 A/B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane. The EQB[1:0] Terminals are converted to SMBus AD2, AD3 inputs. See Table 5. DEMB0, DEMB1 53, 54 I, 4-LEVEL, DEMB[1:0] controls the level of de-emphasis of CHB outputs. The LVCMOS Terminals are defined as DEMB[1:0] only when ENSMB is de-asserted (low). Each of the 4 B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane. The DEMB[1:0] Terminals are converted to AD0, AD1 inputs. See Table 7. MODE_B 21 I, 4-LEVEL, MODE_B control Terminal selects operating modes for the INB-OUTB LVCMOS Channels. Tie 1k Ω to GND = GEN 1,2 and SAS 1,2 Float = Auto Mode Select (for PCIe) Tie 20k Ω to GND = SAS-3 and GEN-3 without De-emphasis Tie 1k Ω to VDD = SAS-3 and GEN-3 with De-emphasis See Table 4. (1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured. Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%. For 3.3V mode operation, VIN Terminal input = 3.3V and the logic "1" reference for the 4-level input is 3.3V. For 2.5V mode operation, VDD Terminal output= 2.5V and the logic "1" reference for the 4-level input is 2.5V. 4 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DS125BR401A |
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