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DP83861VQM-3 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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DP83861VQM-3 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 88 page  3 www.national.com Table of Contents 1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 TP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 E2PROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.6 LED/Interrupt Interface . . . . . . . . . . . . . . . . . . . . . 8 1.7 Device Configuration Interface . . . . . . . . . . . . . . . 9 1.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.9 Power And Ground Pins . . . . . . . . . . . . . . . . . . . 10 1.10 Special Connect Pins . . . . . . . . . . . . . . . . . . . . . . 11 2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Speed/Duplex Mode Selection . . . . . . . . . . . . . . 12 2.2 Manual Mode Configurations . . . . . . . . . . . . . . . . 12 2.3 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 MII/GMII Interface and Speed of Operation . . . . . 15 2.7 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8 Automatic MDI / MDI-X Configuration . . . . . . . . . 16 2.9 Polarity Correction . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 Firmware Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 16 3.0 Design and Layout Guide . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . 17 3.2 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . 18 3.3 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Strapping Options . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 Unused Pins/Reserved Pins . . . . . . . . . . . . . . . . 20 3.7 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 Temperature Considerations . . . . . . . . . . . . . . . . 21 3.9 Pin List and Connections . . . . . . . . . . . . . . . . . . . 21 4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 1000BASE-T Functional Description . . . . . . . . . . 34 4.2 1000BASE-T PCS TX . . . . . . . . . . . . . . . . . . . . . 35 4.3 1000BASE-T PMA TX Block . . . . . . . . . . . . . . . . 36 4.4 PMA Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5 1000BASE-T PCS RX . . . . . . . . . . . . . . . . . . . . . 37 4.6 Gigabit MII (GMII) . . . . . . . . . . . . . . . . . . . . . . . . 38 4.7 ADC/DAC/Timing Subsystem . . . . . . . . . . . . . . . 38 4.8 10BASE-T and 100BASE-TX Transmitter . . . . . . 39 4.9 100BASE-TX Receiver . . . . . . . . . . . . . . . . . . . . 42 4.10 10BASE-T Functional Description . . . . . . . . . . . . 45 4.11 ENDEC Module . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.12 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.13 Status Information . . . . . . . . . . . . . . . . . . . . . . . . 47 4.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.1 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . 49 4.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 68 5.1 DC Electrical Specification . . . . . . . . . . . . . . . . . . 68 5.2 PGM Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 70 5.3 Serial Management Interface Timing . . . . . . . . . 70 5.4 1000 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5 100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.6 Auto-Negotiation Fast Link Pulse (FLP) Timing . . 75 5.7 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.8 Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . 77 5.9 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.0 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.1 CMOS Outputs (GMII/MII and LED) . . . . . . . . . . 79 6.2 TXD± Outputs (sourcing 100BASE-TX) . . . . . . . . 79 6.3 TXD± Outputs (sourcing 1000BASE-T) . . . . . . . . 79 6.4 Idd Measurement Conditions . . . . . . . . . . . . . . . . 79 6.5 GMII Point-to-Point Test Conditions . . . . . . . . . . 79 6.6 GMII Setup and Hold Test Conditions . . . . . . . . 79 7.0 User Information: . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.1 10Mb/s VOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.2 Asymmetrical Pause . . . . . . . . . . . . . . . . . . . . . . 82 7.3 Next Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4 125 MHz Oscillator Operation with Ref_Sel Floating 83 7.5 MDI/MDIXOperationwheninForced10Mb/sand100MB/s 83 7.6 Receive LED in 10 Mb/s Half Duplex mode . . . . 83 8.0 EN Gig PHYTER Frequently Asked Questions: . . . . 84 8.1 Q1: What is the difference between TX_CLK, TX_TCLK, and GTX_CLK? 84 8.2 Q2: What happens to the TX_CLK during 1000 Mb/s operation? Similarly what happens to RXD[4:7] dur- ing 10/100 Mb/s operation? 84 8.3 Q3: What happens to the TX_CLK and RX_CLK dur- ing Auto-Negotiation and during idles? 84 8.4 Q4: Why doesn’t the EN Gig PHYTER complete Auto-Negotiation if the link partner is a forced 1000 Mb/s PHY? 84 8.5 Q5: My two EN Gig PHYTERs won’t talk to each oth- er, but they talk to another vendor’s PHY. 84 8.6 Q6: You advise not to use Manual Master/Slave con- figuration. How come it’s an option? 84 8.7 Q7: How can I write to EN Gig PHYTER expanded address or RAM locations? Why do I need to write to these locations? 84 8.8 Q8: What specific addresses and values do I have to use for each of the functions mentioned in Q7 above? 85 8.9 Q9: How can I do firmware updates? What are some of the benefits of the firmware updates? 85 8.10 Q10: How long does Auto-Negotiation take? . . . 86 8.11 Q11: I know I have good link, but register 0x01, bit 2 “Link Status” doesn’t contain value = ‘1’ indicating good link. 86 8.12 Q12: I have forced 100 Mb/s operation but the 100 Mb/s speed LED doesn’t come on. 86 8.13 Q13: Your reference design shows pull-up or pull- down resistors attached to certain pins, which con- flict with the pull-up or pull-down information speci- fied in the datasheet? 86 8.14 Q14: What are some other applicable documents? 86 8.15 Q15:Howisthemaximumjunctiontemperaturecalculated? 86 8.16 Q16: How do I measure FLP’s? . . . . . . . . . . . . . 86 8.17 Q17: The DP83861 will establish Link in 10 Mb/s and 100Mb/s mode with a Broadcom part, but it will not establish link in 1000 Mb/s mode. When this happens the DP83861’s Link led will blink on and off. 86 8.18 Q18: Why isn’t the Interrupt Pin (Pin 208) an Open Drain Output? 87 9.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 88 |
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