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DS15MB200 Datasheet(PDF) 10 Page - Texas Instruments |
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DS15MB200 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 18 page 15MB200 R2 50: R1 50: 50: 50: LVPECL VT LVPECL R2 150: R1 150: 50: 50: 15MB200 0.1 PF 0.1 PF DS15MB200 SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013 www.ti.com Figure 9. AC Coupled LVPECL to LVDS Interface An AC coupled interface is preferred when transmitter and receiver ground references differ more than 1 V. This is a likely scenario when transmitter and receiver devices are on separate PCBs. Figure 9 illustrates an AC coupled interface between a LVPECL driver and LVDS receiver. R1 and R2, if not present in the driver device(2), provide DC load for the emitter followers and may range between 140-220 ohms for most LVPECL devices for this particular configuration. The DS15MB200 includes an internal 100 ohm resistor to terminate the transmission line for minimal reflections. The signal after AC coupling capacitors will swing around a level set by internal biasing resistors (i.e. fail-safe) which is either VDD/2 or 0 V depending on the actual failsafe implementation. If internal biasing is not implemented, the signal common mode voltage will slowly wander to GND level. Interfacing LVDS to LVPECL An LVDS driver consists of a current source (nominal 3.5mA) which drives a CMOS differential pair. It needs a differential resistive load in the range of 70 to 130 ohms to generate LVDS levels. In a system, the load should be selected to match transmission line characteristic differential impedance so that the line is properly terminated. The termination resistor should be placed as close to the receiver inputs as possible. When interfacing an LVDS driver with a non-LVDS receiver, one only needs to bias the LVDS signal so that it is within the common mode range of the receiver. This may be done by using separate biasing voltage which demands another power supply. Some receivers have required biasing voltage available on-chip (VT, VTT or VBB). Figure 10. DC Coupled LVDS to LVPECL Interface Figure 10 illustrates interface between an LVDS driver and a LVPECL with a VT pin available. R1 and R2, if not present in the receiver(2), provide proper resistive load for the driver and termination for the transmission line, and VT sets desired bias for the receiver. (2) The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device. The LVPECL driver and receiver specification must be reviewed closely to ensure compatibility between the driver and receiver terminations and common mode operating ranges. 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS15MB200 |
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