Channel 1

Channel 0

LI_0

SOA_0

SOB_0

SIA_0

SIB_0

MUX_S0

PREA_0

ENA_0

PREB_0

ENB_0

LO_0

PREL_0

ENL_0

DS15MB200

SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013

www.ti.com

Block Diagram

Figure 2.

PIN DESCRIPTIONS

Pin

WQFN Pin

I/O, Type

Description

Name

Number

SWITCH SIDE DIFFERENTIAL INPUTS

SIA_0+

30

I, LVDS

Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIA_0

−

29

LVPECL compatible.

SIA_1+

19

I, LVDS

Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIA_1

−

20

LVPECL compatible.

SIB_0+

28

I, LVDS

Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIB_0

−

27

LVPECL compatible.

SIB_1+

21

I, LVDS

Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIB_1

−

22

LVPECL compatible.

LINE SIDE DIFFERENTIAL INPUTS

LI_0+

40

I, LVDS

Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LI_0

−

39

LVPECL compatible.

LI_1+

9

I, LVDS

Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LI_1

−

10

LVPECL compatible.

SWITCH SIDE DIFFERENTIAL OUTPUTS

SOA_0+

34

O, LVDS

SOA_0

−

33

SOA_1+

15

O, LVDS

SOA_1

−

16

SOB_0+

32

O, LVDS

SOB_0

−

31

SOB_1+

17

O, LVDS

SOB_1

−

18

LINE SIDE DIFFERENTIAL OUTPUTS

LO_0+

42

O, LVDS

LO_0

−

41

LO_1+

7

O, LVDS

LO_1

−

8

(1)

For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).

(2)

The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15MB200 device have

been optimized for point-to-point backplane and cable applications.

2

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