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DS10CP154A Datasheet(PDF) 3 Page - Texas Instruments |
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DS10CP154A Datasheet(HTML) 3 Page - Texas Instruments |
3 / 22 page DS10CP154A www.ti.com SNLS306C – AUGUST 2008 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Pin Name I/O, Type Pin Description Number IN0+, IN0- , 1, 2, I, LVDS Inverting and non-inverting high speed LVDS input pins. IN1+, IN1-, 4, 5, IN2+, IN2-, 6, 7, IN3+, IN3- 9, 10 OUT0+, OUT0-, 29, 28, O, LVDS Inverting and non-inverting high speed LVDS output pins. OUT1+, OUT1-, 27, 26, OUT2+, OUT2-, 24, 23, OUT3+, OUT3- 22, 21 EN_smb 17 I, LVCMOS System Management Bus (SMBus) mode enable pin. The pin has an internal 20k pull down. When the pin is set to a [1], the device is in the SMBus mode. All SMBus registers are reset when the pin is toggled. S00/SCL, 37, I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed to the OUT0. S01/SDA 36 In the SMBus mode, when the EN_smb = [1], these pins are the SMBus clock input and data I/O pins respectively. S10/ADDR0, 35, I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed to the OUT1. S11/ADDR1 34 In the SMBus mode, when the EN_smb = [1], these pins are the User-Set SMBus Slave Address inputs. S20/ADDR2, 33, I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed to the OUT2. S21/ADDR3 32 In the SMBus mode, when the EN_smb = [1], these pins are the User-Set SMBus Slave Address inputs. S30, S31 13, 14 I, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed to the OUT3. In the SMBus mode, when the EN_smb = [1], these pins are non-functional and should be tied to either logic [0] or [1]. PWDN 38 I, LVCMOS For EN_smb = [0], this is the power down pin. When the PWDN is set to a [0], the device is in the power down mode. The SMBus circuitry can still be accessed provided the EN_smb pin is set to a [1]. In the SMBus mode, the device is powered up by either setting the PWDN pin to [1] OR by writing a [1] to the Control Register D[7] bit ( SoftPWDN). The device will be powered down by setting the PWDN pin to [0] AND by writing a [0] to the Control Register D[7] bit ( SoftPWDN). NC 11, 12, 18, No connect pins. May be left floating. 19, 20, 31, 39, 40 VDD 3, 8, Power Power supply pins. 15,25, 30 GND 16, DAP Power Ground pin and pad (DAP - die attach pad). Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS10CP154A |
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