CDC9171

DVD SYSTEM CLOCK SYNTHESIZER

SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996

3

POST OFFICE BOX 655303

recommended operating conditions (see Note 3)

MIN

MAX

UNIT

VCC

Supply voltage

3

3.6

V

VI

Input voltage (PWRDN only)

0

5.5

V

VIH

High-level input voltage

2

V

VIL

Low-level input voltage

0.8

V

IOH

High-level output current

–8

mA

IOL

Low-level output current

8

mA

TA

Operating free-air temperature

0

70

°C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25°C

MIN

MAX

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNIT

VIK

VCC = 3 V,

II = –18 mA

–1.2

–1.2

V

VOH

VCC = 3 V,

IOH = –8 mA

2.4

2.4

V

VOL

VCC = 3 V,

IOL = 8 mA

0.4

0.4

V

II†

VCC = 3.6 V,

VI = VCC or GND

±1

±1

µA

ICC

VCC = 3.6 V,

IO = 0

Outputs active

(PWRDN = H)

20

35

35

mA

ICC

CC

,

VI = VCC or GND

O

Outputs low

(PWRDN = L)

5

10

10

mA

Ci†

VI = 3 V or 0

7

pF

Co

VO = 3 V or 0

8

pF

† Except for crystal input (1X1)

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

UNIT

Stabilization time‡

After PWRDN

↑

5

ms

Stabilization time‡

After power up

5

ms

‡ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed-frequency, fixed-phase reference signal must be present at 1X1.

switching characteristics over recommended free-air temperature range for 3-V outputs (see

PARAMETER

VCC = 3.3 V,

TA = 25°C

VCC = 3 V to 3.6 V,

TA = 0°C to 70°C

UNIT

MIN

MAX

MIN

MAX

Jitter

FCLK1

±200

ps

Jitter

All other outputs

±250

ps

Duty cycle

Any output

45%

55%

tr¶

Any output (CL = 20 pF)

2.5

ns

tf¶

Any output (CL = 20 pF)

2.5

ns

§ Specifications are applicable only after the PLL stabilization time has elapsed.

¶ Rise and fall times are characterized using the test circuit shown in Figure 1.