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CDC925DL Datasheet(PDF) 1 Page - Texas Instruments

Part # CDC925DL
Description  133MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDC925DL Datasheet(HTML) 1 Page - Texas Instruments

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CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Supports Pentium III™ Class Motherboards
D Uses a 14.318-MHz Crystal Input to
Generate Multiple Output Frequencies
D Includes Spread Spectrum Clocking (SSC),
0.34% Downspread for Reduced EMI
Performance
D Power Management Control Terminals
D Low Output Skew and Jitter for Clock
Distribution
D 2.5-V and 3.3-V Supplies
D Generates the Following Clocks:
– 4 CPU (2.5 V, 100/133 MHz)
– 7 PCI (3.3 V, 33.3 MHz)
– 1 PCI_F (Free Running, 3.3 V, 33.3 MHz)
– 2 CPU/2 (2.5 V, 50/66 MHz)
– 3 APIC (2.5 V, 16.67 MHz)
– 4 3V66 (3.3 V, 66 MHz)
– 2 REF (3.3 V, 14.318 MHz)
– 1 48MHz (3.3 V, 48 MHz)
D Packaged in 56-Pin SSOP Package
D Designed for Use with TI’s Direct Rambus™
Clock Generators (CDCR81, CDCR82,
CDCR83)
description
The CDC925 is a clock synthesizer/driver that
generates system clocks necessary to support
Intel Pentium III systems on CPU, CPU_DIV2,
3V66, PCI, APIC, 48MHz, and REF clock signals.
All output frequencies are generated from a
14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two
phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz
clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components.
The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All
outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100.
The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN
terminal, the device operates normally, but when a logical low-level input is applied, the device powers down
completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP or
CPU_STOP, the outputs operate normally. With a low-level applied to the PCI_STOP or CPU_STOP terminals,
the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state.
The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding
setting for SEL133/100 control input. The PCI bus frequency is fixed to 33MHz.
Copyright
© 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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GND
REF0
REF1
VDD3.3V
XIN
XOUT
GND
PCI_F
PCI1
VDD3.3V
PCI2
PCI3
GND
PCI4
PCI5
VDD3.3V
PCI6
PCI7
GND
GND
3V66(0)
3V66(1)
VDD3.3V
GND
3V66(2)
3V66(3)
VDD3.3V
SEL133/100
VDD2.5V
APIC2
APIC1
APIC0
GND
VDD2.5V
CPU_DIV2(1)
CPU_DIV2(0)
GND
VDD2.5V
CPU3
CPU2
GND
VDD2.5V
CPU1
CPU0
GND
VDD3.3V
GND
PCI_STOP
CPU_STOP
PWR_DWN
SPREAD
SEL1
SEL0
VDD3.3V
48MHz
GND
DL PACKAGE
(TOP VIEW)
Intel and Pentium III are trademarks of Intel Corporation.
Direct Rambus and Rambus are trademarks of Rambus Inc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


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