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DAC7760 Datasheet(PDF) 30 Page - Texas Instruments |
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DAC7760 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 63 page  30 DAC7760, DAC8760 SBAS528B – JUNE 2013 – REVISED JUNE 2016 www.ti.com Product Folder Links: DAC7760 DAC8760 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated 8.3.5 Digital Power Supply An internally generated 4.6-V supply capable of driving up to 10 mA can be output on DVDD by leaving the DVD- EN pin unconnected. This supply eases the system power supply design especially when an isolation barrier is required to cross and generate the digital supply. It can be used to drive isolation components used for the digital data lines and other miscellaneous components like references and temp sensors. See Figure 96 for an example application. If an external supply is preferred, the DVDD pin (which can be driven up to 5.5 V in this case) can be made into an input by tying DVDD-EN to GND (see Electrical Characteristics for detailed specifications). 8.3.6 DAC Clear The DAC has an asynchronous clear function through the CLR pin, which is active-high and allows the voltage output to be cleared to either zero-scale code or midscale code. This action is user-selectable through the CLR- SEL pin or the CLRSEL bit of the Table 17, as Table 2 describes. The CLR-SEL pin and CLRSEL register are ORed together. The current output clears to the bottom of its preprogrammed range. When the CLR signal returns to low, the output remains at the cleared value. The pre-clear value can be restored by pulsing the LATCH signal without clocking any data. A new value cannot be programmed until the CLR pin returns to low. Note that in dual-output mode, the value that the DAC data register is cleared to follows the settings for the voltage output mode. Table 2. CLR-SEL Options CLR-SEL OUTPUT VALUE UNIPOLAR OUTPUT RANGE BIPOLAR OUTPUT RANGE 0 0 V 0 V 1 Midscale Negative full-scale In addition to defining the output value for a clear operation, the CLRSEL bit and the CLR-SEL pin also define the default output value. During the selection of a new voltage range, the output value corresponds to the definitions given in Table 7. To avoid glitches on the output, disable the output by writing a 0 to the OUTEN bit of the Table 17 before changing the voltage range. When the OUTEN bit is set to 1, the output goes to the default value as defined by the CLRSEL bit and the CLR-SEL pin. 8.3.7 Power-Supply Sequence The DACx760 has internal power on reset (POR) circuitry for both the digital DVDD and analog AVDD supplies. This circuitry makes sure that the internal logic and power-on state of the DAC power up to the proper state independent of the supply sequence. While there is no required supply power-on sequence, the recommendation is to first have the digital DVDD supply come up, followed by the analog supplies, AVDD and AVSS. AVSS is powered assuming a negative supply is being used. Otherwise, AVSS is tied to GND. 8.3.8 Power-On Reset The DACx760 incorporates two internal POR circuits for the DVDD and AVDD supplies. The DVDD and AVDD POR signals are ANDed together so that both supplies must be at their minimal specified values for the device to not be in a reset condition. These POR circuits initialize internal logic and registers as well as set the analog outputs to a known state while the device supplies are ramping. All registers are reset to their default values with the default value of the data register being determined by the CLR-SEL pin. The behavior of IOUT and VOUT is described in their respective sections. Typically the POR function can be ignored as long as the device supplies power up and maintain the specified minimum voltage levels. However, in the case of supply drop or brownout, the DACx760 can have an internal POR reset event or lose digital memory integrity. Figure 85 represents the threshold levels for the internal POR for both the DVDD and AVDD supplies. |
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