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DP8238J Datasheet(PDF) 5 Page - Texas Instruments |
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DP8238J Datasheet(HTML) 5 Page - Texas Instruments |
5 / 8 page Timing Diagram TLF6825 – 5 VOLTAGE MEASUREMENT POINTS D0–D7 (when outputs) Logic ‘‘0’’ e 08V Logic ‘‘0’’ e 08V Logic ‘‘1’’ e 30V All other signals measured at 15V Advanced IOW MEMW for 8238 only Functional Pin Definitions The following describes the function of all of the DP8228 DP8228M DP8238DP8238M pinouts Some of these de- scriptions reference internal circuits INPUT SIGNALS Status Strobe (STSTB) Activated (low) at the start of each new machine cycle The STSTB input is used to store a status word (refer to chart) from the 8080A microprocessor into the internal status latch of the DP8228 DP8238 The status word is latched when the STSTB returns to the high state The 8080A outputs this status word onto its data bus during the first state (SYNC interval) of each machine cycle Data Bus In (DBIN) When high indicates that the 8080A data bus is in the input mode The DBIN signal is used to gate data from memory or an inputoutput device onto the data bus Write (WR) When low indicates that the data on the 8080A data bus are stable for WRITE memory or output operation Hold Acknowledge (HLDA) When high indicates that the 8080A data and address buses will go to their high imped- ance state When in the data bus read mode DBIN input in the high state a high HLDA input will latch the data bus information into the driver circuits and gate off the applica- ble control signal IOR MEMR or INTA (return to the out- put high state) Bus Enable (BUSEN) Asynchronous DMA input to the in- ternal gating array When low normal operation of the inter- nal bidirectional bus driver and gating array occurs When high the bus driver and gating array are driven to their high impedance state VCC Supply a5V Ground 0V reference OUTPUT SIGNALS Memory Read (MEMR) When low signals data to be load- ed in from memory The MEMR signal is generated by strob- ing in status word 1 2 or 4 (Refer to status word chart) Memory Write (MEMW) When low signals data to be stored in memory The MEMW signal is generated for the DP8238 by strobing in status word 3 or 5 (Refer to status word chart) For the DP8228 the MEMW signal is generated by gating a low-level WR input with the strobed in status word3or5 InputOutput Read (IOR) When low signals data to be loaded in from an addressed inputoutput device The IOR signal is generated by strobing in status word 6 InputOutput Write (IOW) When low signals data to be transferred to an addressed inputoutput device The IOW signal for the DP8238 is generated by strobing in status word 7 For the DP8238 the IOW signal is generated by gating in a low-level WR input with the strobed in status word 7 Interrupt Acknowledge (INTA) When low indicates that an interrupt has been acknowledged by the 8080A micro- processor The INTA signal is generated by strobing in staus word 8 or 10 Signal Level Interrupt (RST 7) When the INTA output is tied to 12V througha1kX resistor strobing in status word 8 or 10 will cause the CPU data bus outputs when active to go to the high state INPUTOUTPUT SIGNALS CPU Data (D7–D0) Bus This bus comprises eight TRI-STATE inputoutput lines that connect to the 8080A microprocessor The bus provides bidirectional communica- 4 |
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