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DLP4710 Datasheet(PDF) 4 Page - Texas Instruments |
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DLP4710 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 39 page 4 DLP4710 DLPS056B – NOVEMBER 2014 – REVISED JULY 2016 www.ti.com Product Folder Links: DLP4710 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Pin Functions – Connector Pins(1) (continued) PIN TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm) NAME NO. (3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required. D_AP(4) J6 I SubLVDS Double Data, Positive 3.23 D_AP(5) L6 I SubLVDS Double Data, Positive 3.87 D_AP(6) G6 I SubLVDS Double Data, Positive 6.32 D_AP(7) L4 I SubLVDS Double Data, Positive 1.84 D_BN(0) G27 I SubLVDS Double Data, Negative 2.51 D_BN(1) E26 I SubLVDS Double Data, Negative 4.43 D_BN(2) D28 I SubLVDS Double Data, Negative 2.76 D_BN(3) D26 I SubLVDS Double Data, Negative 5.47 D_BN(4) L25 I SubLVDS Double Data, Negative 4.85 D_BN(5) K25 I SubLVDS Double Data, Negative 4.10 D_BN(6) L28 I SubLVDS Double Data, Negative 2.53 D_BN(7) K27 I SubLVDS Double Data, Negative 2.76 D_BP(0) F27 I SubLVDS Double Data, Positive 2.51 D_BP(1) E27 I SubLVDS Double Data, Positive 4.43 D_BP(2) D27 I SubLVDS Double Data, Positive 2.76 D_BP(3) D25 I SubLVDS Double Data, Positive 5.47 D_BP(4) L26 I SubLVDS Double Data, Positive 4.85 D_BP(5) J25 I SubLVDS Double Data, Positive 4.10 D_BP(6) K28 I SubLVDS Double Data, Positive 2.53 D_BP(7) J27 I SubLVDS Double Data, Positive 2.76 DCLK_AN J3 I SubLVDS Double Clock, Negative 3.77 DCLK_AP K3 I SubLVDS Double Clock, Positive 3.77 DCLK_BN H26 I SubLVDS Double Clock, Negative 2.98 DCLK_BP H27 I SubLVDS Double Clock, Positive 2.98 CONTROL INPUTS LS_WDATA D3 I LPSDR(1) Single Write data for low speed interface. 1.20 LS_CLK C3 I LPSDR Single Clock for low-speed interface 1.20 DMD_DEN_ARSTZ B6 I LPSDR Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 4.19 LS_RDATA_A C6 O LPSDR Single Read data for low-speed interface 3.93 LS_RDATA_B C4 O LPSDR Single Read data for low-speed interface 2.57 POWER VBIAS(3) B27 Power Supply voltage for positive bias level at micromirrors 24.51 VBIAS(3) B4 Power 24.51 VOFFSET(3) B2 Power Supply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes. Supply voltage for offset level at micromirrors. 49.56 VOFFSET(3) C29 Power 49.56 VRESET B28 Power Supply voltage for negative reset level at micromirrors. 24.82 VRESET B3 Power 24.82 |
Similar Part No. - DLP4710_16 |
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Similar Description - DLP4710_16 |
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