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DDC232CK Datasheet(PDF) 10 Page - Texas Instruments |
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DDC232CK Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 34 page  0.10mF +5V 10kW 10mF 4 3 2 3 1 2 7 6 + 0.10mF 10mF + OPA350 0.47mF +5V To VREF Pin on the DDC232 REF3140 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com charge needed by the ∆Σ converter. For an Integration Capacitors integration time of 333ms, this charge translates to an average VREF current of approximately 325mA. The There are seven different capacitors available on-chip amount of charge needed by the ∆Σ converter is for both sides of every channel in the DDC232. These independent of the integration time; therefore, internal capacitors are trimmed in production to increasing the integration time lowers the average achieve the specified performance for range error of current. For example, an integration time of 800ms the DDC232. The range control bits (Range[2:0]) lowers the average VREF current to 135mA. change the capacitor value for all integrators. Consequently, all inputs and both sides of each input It is critical that VREF be stable during the different will always have the same full-scale range. Table 4 modes of operation (see Figure 5). The ∆Σ converter shows the capacitor value selected for each range measures the voltage on the integrator with respect selection. to VREF. Since the integrator capacitors are initially reset to VREF, any drop in VREF from the time the Table 4. Range Selection capacitors are reset to the time when the converter measures the integrator output will introduce an RANGE CONTROL BITS INPUT CF RANGE offset. It is also important that VREF be stable over RANGE Range[2] Range[1] Range[0] (pF, typ) (pC, typ) longer periods of time because changes in VREF 0 0 0 0 3 –0.04 to 12.5 correspond directly to changes in the full-scale range. 1 0 0 1 12.5 –0.2 to 50 Finally, VREF should introduce as little additional 2 0 1 0 25 –0.4 to 100 noise as possible. 3 0 1 1 37.5 –0.6 to 150 For these reasons, it is strongly recommended that 4 1 0 0 50 –0.8 to 200 the external reference source be buffered with an 5 1 0 1 62.5 –0.1 to 250 operational amplifier, as shown in Figure 6. In this 6 1 1 0 75 –1.2 to 300 circuit, the voltage reference is generated by a 7 1 1 1 87.5 –1.4 to 350 +4.096V reference. A low-pass filter to reduce noise connects the reference to an operational amplifier configured as a buffer. This amplifier should have low Voltage Reference noise and input/output common-mode ranges that The external voltage reference is used to reset the support VREF. Even though the circuit in Figure 6 integration capacitors before an integration cycle might appear to be unstable due to the large output begins. It is also used by the ∆Σ converter while the capacitors, it works well for most operational converter is measuring the voltage stored on the amplifiers. It is not recommended that series integrators after an integration cycle ends. During this resistance be placed in the output lead to improve sampling, the external reference must supply the stability since this can cause a drop in VREF, which produces large offsets. Figure 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation 10 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 |
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