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DDC112UK/1K Datasheet(PDF) 9 Page - Texas Instruments |
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DDC112UK/1K Datasheet(HTML) 9 Page - Texas Instruments |
9 / 34 page DDC112 9 SBAS085B www.ti.com DEVICE OPERATION Basic Integration Cycle The fundamental topology of the front end of the DDC112 is a classical analog integrator, as shown in Figure 3. In this diagram, only Input 1 is shown. This representation of the input stage consists of an operational amplifier, a selectable feedback capacitor network (CF), and several switches that implement the integration cycle. The timing relationships of all of the switches shown in Figure 3 are illustrated in Figure 4. Figure 4 is used to conceptualize the operation of the integrator input stage of the DDC112 and should not be used as an exact timing tool for design. Block diagrams of the reset, integrate, converter, and wait states of the inte- grator section of the DDC112 are shown in Figure 5. This internal switching network is controlled externally with the convert command (CONV), range selection pins (RANGE0- RANGE2), and the system clock (CLK). For the best noise performance, CONV must be synchronized with the rising edge of CLK. It is recommended CONV toggle within ±10ns of the rising edge of CLK. The noninverting inputs of the integrators are internally referenced to ground. Consequently, the DDC112 analog ground should be as clean as possible. The range switches, along with the internal and external capacitors (CF) are shown in parallel between the inverting input and output of the operational amplifier. Table I shows the value of the integration capacitor (CF) for each range. At the beginning of a conversion, the switches SA/D, SINTA, SINTB, SREF1, SREF2, and SRESET are set (see Figure 4). At the completion of an A/D conversion, the charge on the integration capacitor (CF) is reset with SREF1 and CF INPUT RANGE RANGE2 RANGE1 RANGE0 (pF, typ) (pC, typ) 0 0 0 External Up to 1000 12.5 to 250 0 0 1 12.5 –0.2 to 50 01 0 25 –0.4 to 100 0 1 1 37.5 –0.6 to 150 10 0 50 –0.8 to 200 1 0 1 62.5 –0.1 to 250 11 0 75 –1.2 to 300 1 1 1 87.5 –1.4 to 350 TABLE I. Range Selection of the DDC112. FIGURE 3. Basic Integrator Configuration for Input 1 Shown with a 250pC (CF = 62.5pF) Input Range. SRESET (see Figures 4 and 5a). This is done during the reset time. In this manner, the selected capacitor is charged to the reference voltage, VREF. Once the integration capacitor is charged, SREF1, and SRESET are switched so that VREF is no longer connected to the amplifier circuit while it waits to begin integrating (see Figure 5b). With the rising edge on CONV, SINTA closes which begins the integration of Channel A. This puts the integrator stage into its integrate mode (see Figure 5c). Charge from the input signal is collected on the integration capacitor causing the voltage output of the amplifier to decrease. A falling edge CONV stops the integration by switching the input signal from side A to side B (SINTA and SINTB). Prior to the falling edge of CONV, the signal on side B was converted by the A/D converter and reset during the time that side A was integrating. With the falling edge of CONV, side B starts integrating the input signal. Now the output voltage of side A’s operational amplifier is presented to the input of the ∆Σ A/D converter (see Figure 5d). 50pF CAP1A CAP1A 25pF 12.5pF V REF RANGE2 RANGE1 RANGE0 To Converter S RESET S REF2 S A/D1A S INTA S REF1 S INTB IN1 ESD Protection Diode Input Current Integrator A Integrator B (same as A) Photodiode |
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