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DAC8550IBDGKRG4 Datasheet(PDF) 5 Page - Texas Instruments |
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DAC8550IBDGKRG4 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 31 page  5 DAC8550 www.ti.com SLAS476F – MARCH 2006 – REVISED MARCH 2016 Product Folder Links: DAC8550 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated (1) Linearity calculated using a reduced code range of –32283 to 32063; output unloaded. (2) Specified by design and characterization, not production tested. 6.5 Electrical Characteristics VDD = 2.7 V to 5.5 V, –40°C to 105°C range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE(1) Resolution 16 Bits EL Relative accuracy Measured by line passing through codes –32283 and 32063 DAC8550 ±3 ±12 LSB DAC8550B ±3 ±8 ED Differential nonlinearity 16-bit monotonic ±0.25 ±1 LSB EO Zero-code error Measured by line passing through codes –32283 and 32063 ±2 ±12 mV EFS Full-scale error Measured by line passing through codes –32283 and 32063 ±0.05% ±0.5% mV EG Gain error Measured by line passing through codes –32283 and 32063 ±0.02% ±0.2% mV Zero-code error drift ±5 μV/°C Gain temperature coefficient ±1 ppm of FSR/°C PSRR Power-supply rejection ratio RL = 2 kΩ, CL = 200 pF 0.75 mV/V OUTPUT CHARACTERISTICS(2) VO Output voltage range 0 VREF V tSD Output voltage settling time To ±0.003% FSR, 1200h to 8D00h, RL = 2 kΩ, 0 pF < CL < 200 pF 8 10 μs RL = 2 kΩ, CL = 500 pF 12 SR Slew rate 1.8 V/ μs Capacitive load stability RL = ∞ 470 pF RL = 2 kΩ 1000 Code change glitch impulse 1 LSB change around major carry 0.1 nV-s Digital feedthrough SCLK toggling, FSYNC high 0.1 nV-s zO DC output impedance At mid-code input 1 Ω IOS Short-circuit current VDD = 5 V 50 mA VDD = 3 V 20 tON Power-up time Coming out of power-down mode, VDD = 5 V 2.5 μs Coming out of power-down mode, VDD = 3 V 5 AC PERFORMANCE SNR Signal-to-noise ratio BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz, 1st 19 harmonics removed for SNR calculation 95 dB THD Total harmonic distortion BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz, 1st 19 harmonics removed for SNR calculation –85 dB SFDR Spurious-free dynamic range BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz, 1st 19 harmonics removed for SNR calculation 87 dB SINAD Signal-to-noise and distortion BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz, 1st 19 harmonics removed for SNR calculation 84 dB REFERENCE INPUT VREF Reference voltage 0 VDD V II(REF) Reference current input range VREF = VDD = 5 V 40 75 μA VREF = VDD = 3.6 V 30 45 zI(REF) Reference input impedance 125 k Ω LOGIC INPUTS (2) Input current ±1 μA VIL Low-level input voltage VDD = 5 V 0.3 × VDD V VDD = 3 V 0.1 × VDD VIH High-level input voltage VDD = 5 V 0.7 × VDD V VDD = 3 V 0.9 × VDD Pin capacitance 3 pF |
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