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74LVC2G08DC Datasheet(PDF) 11 Page - Panasonic Semiconductor |
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74LVC2G08DC Datasheet(HTML) 11 Page - Panasonic Semiconductor |
11 / 15 page 2004 Sep 15 11 Philips Semiconductors Product specification Dual 2-input AND gate 74LVC2G08 PACKAGE OUTLINES UNIT A1 A max. A2 A3 bp L HE Lp wy v ce D(1) E(1) Z(1) θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.00 0.95 0.75 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.70 0.35 8 ° 0 ° 0.13 0.1 0.2 0.5 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 0.47 0.33 SOT505-2 - - - 02-01-16 w M bp D Z e 0.25 14 8 5 θ A2 A1 Lp (A3) detail X A L HE E c v M A X A y 2.5 5 mm 0 scale TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 1.1 pin 1 index |
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