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DAC7615U Datasheet(PDF) 10 Page - Texas Instruments |
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DAC7615U Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 17 page  ® 10 DAC7615 REFERENCE INPUTS The reference inputs, VREFL and VREFH, can be any voltage between VSS + 2.25V and VDD – 2.25V provided that VREFH is at least 1.25V greater than VREFL. The minimum output of each DAC is equal to VREFL – 1LSB plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to VREFH plus a similar offset voltage. Note that VSS (the negative power supply) must either be connected to ground or must be in the range of – 4.75V to –5.25V. The voltage on VSS sets several bias points within the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed. The current into the reference inputs depends on the DAC output voltages and can vary from a few microamps to approximately 0.6 milliamp. Bypassing the reference volt- age or voltages with a 0.1 µF capacitor placed as close as possible to the DAC7615 package is strongly recommended. DIGITAL INTERFACE Figure 3 and Table I provide the basic timing for the DAC7615. The interface consists of a serial clock (CLK), serial data (SDI), a load register signal (LOADREG), and a “load all DAC registers” signal (LOADDACS). In addition, a chip select (CS) input is available to enable serial commu- nication when there are multiple serial devices. An asyn- SYMBOL DESCRIPTION MIN TYP MAX UNITS tDS Data Valid to CLK Rising 25 ns tDH Data Held Valid after CLK Rises 20 ns tCH CLK HIGH 30 ns tCL CLK LOW 50 ns tCSS CS LOW to CLK Rising 55 ns tCSH CLK HIGH to CS Rising 15 ns tLD1 LOADREG HIGH to CLK Rising 40 ns tLD2 CLK Rising to LOADREG LOW 15 ns tLDRW LOADREG LOW Time 45 ns tLDDW LOADDACS LOW Time 45 ns tRSSH RESETSEL Valid to RESET LOW 25 ns tRSTW RESET LOW Time 70 ns tS Settling Time 10 µs FIGURE 3. DAC7615 Timing. chronous reset input (RESET) is provided to simplify start- up conditions, periodic resets, or emergency resets to a known state. The DAC code and address are provided via a 16-bit serial interface as shown in Figure 3. The first two bits select the input register that will be updated when LOADREG goes LOW (see Table II). The next two bits are not used. The last 12 bits are the DAC code which is provided, most significant bit first. TABLE I. Timing Specifications (TA = –40°C to +85°C). A1 (MSB) (LSB) SDI CLK CS LOADREG A0 X X D11 D10 D9 D3 D2 D1 D0 SDI CLK LOADDACS RESET V OUT tcss t LD1 t CL t CH t DS t DH t LD2 t LDRW t LDDW t S t RSTW t RSSH t CSH t S 1 LSB ERROR BAND 1 LSB ERROR BAND RESETSEL |
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