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74LVC1G80GW Datasheet(PDF) 10 Page - Panasonic Semiconductor |
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74LVC1G80GW Datasheet(HTML) 10 Page - Panasonic Semiconductor |
10 / 18 page 2004 Sep 10 10 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 Note 1. All typical values are measured at Tamb =25 °C. Tamb = −40 °C to +125 °C tPHL/tPLH propagation delay CP to Q see Figs 6 and 8 1.65 to 1.95 1.0 − 13.0 ns 2.3 to 2.7 0.5 − 9.0 ns 2.7 0.5 − 8.0 ns 3.0 to 3.6 0.9 − 6.5 ns 4.5 to 5.5 0.5 − 6.0 ns tsu set-up time D to CP see Figs 7 and 8 1.65 to 1.95 2.3 −− ns 2.3 to 2.7 1.5 −− ns 2.7 1.5 −− ns 3.0 to 3.6 1.3 −− ns 4.5 to 5.5 1.1 −− ns th hold time D to CP see Figs 7 and 8 1.65 to 1.95 0 −− ns 2.3 to 2.7 0 −− ns 2.7 0.5 −− ns 3.0 to 3.6 0.9 −− ns 4.5 to 5.5 0.5 −− ns tW clock pulse with HIGH or LOW see Figs 7 and 8 1.65 to 1.95 3.0 −− ns 2.3 to 2.7 2.5 −− ns 2.7 2.5 −− ns 3.0 to 3.6 2.5 −− ns 4.5 to 5.5 2.0 −− ns fmax maximum clock pulse frequency see Figs 7 and 8 1.65 to 1.95 160 −− MHz 2.3 to 2.7 160 −− MHz 2.7 160 −− MHz 3.0 to 3.6 160 −− MHz 4.5 to 5.5 200 −− MHz SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) |
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