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74LCX245 Datasheet(PDF) 1 Page - STMicroelectronics

Part No. 74LCX245
Description  LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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74LCX245 Datasheet(HTML) 1 Page - STMicroelectronics

 
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September 2004
s
5V TOLERANT INPUTS AND OUTPUTS
s
HIGH SPEED:
tPD = 7.0 ns (MAX.) at VCC = 3V
s
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
s
PCI BUS LEVELS GUARANTEED AT 24 mA
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
s
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX245 is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
This IC is intended for two way asynchronous
communication between data buses; the direction
of data transmission is determined by DIR input.
The enable input G can be used to disable the
device so that the buses are effectively isolated.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z state must
be held HIGH or LOW.
74LCX245
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER
(3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
74LCX245MTR
TSSOP
74LCX245TTR
TSSOP
SOP
Rev. 4


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