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DAC124S085CIMM Datasheet(PDF) 7 Page - Texas Instruments

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Part No. DAC124S085CIMM
Description  DAC124S085 12-Bit Micro Power Quad Digital-to-Analog Converter With Rail-to-Rail Output
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC124S085CIMM Datasheet(HTML) 7 Page - Texas Instruments

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7
DAC124S085
www.ti.com
SNAS348G – MAY 2006 – REVISED APRIL 2016
Product Folder Links: DAC124S085
Submit Documentation Feedback
Copyright © 2006–2016, Texas Instruments Incorporated
Electrical Characteristics (continued)
TA = 25°C, VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, and input code range 48 to 4047 (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
PN
Normal supply power
fSCLK = 30 MHz,
output unloaded,
VA = 2.7 V to 3.6 V
TA = 25°C
1.1
mW
–40°C
≤ TA ≤ 105°C
1.7
fSCLK = 30 MHz,
output unloaded,
VA = 4.5 V to 5.5 V
TA = 25°C
2.4
mW
–40°C
≤ TA ≤ 105°C
3.6
fSCLK = 0 MHz,
output unloaded
VA = 2.7V to 3.6 V
1
mW
VA = 4.5 V to 5.5 V
2.2
mW
PPD
Power-down supply
power(2)
All PD modes, output
unloaded,
SYNC = DIN = 0 V
after PD mode loaded
VA = 2.7 V to 3.6 V
0.3
3.6
µW
VA = 4.5 V to 5.5 V
0.8
5.5
µW
(1)
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing
Quality Level).
(2)
This parameter is ensured by design and/or characterization and is not tested in production.
7.6 Timing Requirements
TA = 25°C, VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, and input code range 48 to 4047 (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
fSCLK
SCLK frequency
TA = 25°C
40
MHz
–40°C
≤ TA ≤ 105°C
30
ts
Output voltage settling time(2)
400h to C00h
code change
RL = 2 kΩ, CL = 200 pF
TA = 25°C
6
µs
–40°C
≤ TA ≤ 105°C
8.5
SR
Output slew rate
1
V/µs
Glitch impulse
Code change from 800h to 7FFh
12
nV-sec
Digital feedthrough
0.5
nV-sec
Digital crosstalk
1
nV-sec
DAC-to-DAC crosstalk
3
nV-sec
Multiplying bandwidth
VREFIN = 2.5 V ± 0.1 Vpp
160
kHz
Total harmonic distortion
VREFIN = 2.5 V ± 0.1 Vpp
input frequency = 10 kHz
70
dB
tWU
Wake-up time
VA = VREF = 3 V
6
µs
VA = VREF = 5 V
39
µs
1/fSCLK
SCLK cycle time
TA = 25°C
25
ns
–40°C
≤ TA ≤ 105°C
33
tCH
SCLK high time
TA = 25°C
7
ns
–40°C
≤ TA ≤ 105°C
10
tCL
SCLK low time
TA = 25°C
7
ns
–40°C
≤ TA ≤ 105°C
10
tSS
SYNC set-up time
prior to SCLK falling edge
TA = 25°C
4
ns
–40°C
≤ TA ≤ 105°C
10
tDS
Data set-up time
prior to SCLK falling edge
TA = 25°C
1.5
ns
–40°C
≤ TA ≤ 105°C
3.5
tDH
Data hold time
after SCLK falling edge
TA = 25°C
1.5
ns
–40°C
≤ TA ≤ 105°C
3.5
tCFSR
SCLK fall
prior to rise of SYNC
TA = 25°C
0
ns
–40°C
≤ TA ≤ 105°C
3


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