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DAC124S085 Datasheet(PDF) 3 Page - Texas Instruments

Part No. DAC124S085
Description  DAC124S085 12-Bit Micro Power Quad Digital-to-Analog Converter With Rail-to-Rail Output
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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DAC124S085 Datasheet(HTML) 3 Page - Texas Instruments

 
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ExposedPad
1
VA
10
SCLK
2
VOUTA
9
SYNC
3
VOUTB
8
DIN
4
VOUTC
7
VREFIN
5
VOUTD
6
GND
1
VA
10
SCLK
2
VOUTA
9
SYNC
3
VOUTB
8
DIN
4
VOUTC
7
VREFIN
5
VOUTD
6
GND
3
DAC124S085
www.ti.com
SNAS348G – MAY 2006 – REVISED APRIL 2016
Product Folder Links: DAC124S085
Submit Documentation Feedback
Copyright © 2006–2016, Texas Instruments Incorporated
5 Description (continued)
A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a
valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three
different termination options.
The low power consumption and small packages of the DAC124S085 make it an excellent choice for use in
battery-operated equipment.
The DAC124S085 is one of a family of pin-compatible DACs, including the 8-bit DAC084S085 and the 10-bit
DAC104S085. The DAC124S085 operates over the extended industrial temperature range of
−40°C to 105°C.
6 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
DSC Package
10-Pin WSON
Top View
(1)
G = Ground, I = Input, O = Output, and S = Supply
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
1
VA
S
Power supply input. Must be decoupled to GND.
2
VOUTA
O
Channel A analog output voltage.
3
VOUTB
O
Channel B analog output voltage.
4
VOUTC
O
Channel C analog output voltage.
5
VOUTD
O
Channel D analog output voltage.
6
GND
G
Ground reference for all on-chip circuitry.
7
VREFIN
I
Unbuffered reference voltage shared by all channels. Must be decoupled to GND.
8
DIN
I
Serial data input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the
fall of SYNC.
9
SYNC
I
Frame synchronization input for the data input. When this pin goes low, it enables the input shift
register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock
cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC
acts as an interrupt and the write sequence is ignored by the DAC.
10
SCLK
I
Serial clock input. Data is clocked into the input shift register on the falling edges of this pin.
11
PAD
(WSON only)
G
Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB
offers optimal thermal performance and enhances package self-alignment during reflow.


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