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DAC124S085 Datasheet(PDF) 17 Page - Texas Instruments
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DAC124S085 Datasheet(HTML) 17 Page - Texas Instruments
/ 32 page
A0 OP1 OP0 D11 D10 D9
0 0 Write to specified register but do not update outputs.
0 1 Write to specified register and update outputs.
1 0 Write to all registers and update outputs.
1 1 Power-down outputs.
0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D
SNAS348G – MAY 2006 – REVISED APRIL 2016
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Copyright © 2006–2016, Texas Instruments Incorporated
Figure 30. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift
register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and
there is no change in the mode of operation or in the DAC output voltages.
8.5.3 DSP or Microprocessor Interfacing
Interfacing the DAC124S085 to microprocessors and DSPs is quite simple. The following guidelines are offered
to hasten the design process.
22.214.171.124 ADSP-2101 or ADSP2103 Interfacing
Figure 31 shows a serial interface between the DAC124S085 and the ADSP-2101/ADSP2103. The DSP must be
set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and must be configured for Internal Clock Operation, Active-Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
Figure 31. ADSP-2101/2103 Interface
126.96.36.199 80C51 or 80L51 Interface
A serial interface between the DAC124S085 and the 80C51/80L51 microcontroller is shown in Figure 32. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is transmitted to the DAC124S085. Because the 80C51/80L51 transmits 8-
bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must
be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of
data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the
80C51/80L51 transmits data with the LSB first while the DAC124S085 requires data with the MSB first.
Figure 32. 80C51/80L51 Interface
188.8.131.52 68HC11 Interface
A serial interface between the DAC124S085 and the 68HC11 microcontroller is shown in Figure 33. The SYNC
line of the DAC124S085 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.
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