SN54ALVTH16601, SN74ALVTH16601

2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES143A – SEPTEMBER 1998 – REVISED JULY 1999

8

POST OFFICE BOX 655303

(unless otherwise noted) (see Figure 1)

SN54ALVTH16601

SN74ALVTH16601

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

150

150

MHz

t

Pulse duration

LE high

1.8

1.8

ns

tw

Pulse duration

CLK high or low

2.3

2.3

ns

A or B before CLK

↑

Data high

4

4

A or B before CLK

↑

Data low

5.2

5.2

t

Setup time

A or B before LE

↓

CLK high

0.7

0.7

ns

tsu

Setup time

A or B before LE

↓

CLK low

0.9

0.9

ns

CLKEN before CLK

↑

Data high

1.7

1.7

CLKEN before CLK

↑

Data low

2.3

2.3

A or B after CLK

↑

Data high

0.5

0.5

A or B after CLK

↑

Data low

0.5

0.5

th

Hold time

A or B after LE

↓

CLK high

2.3

2.3

ns

th

Hold time

A or B after LE

↓

CLK low

2.4

2.4

ns

CLKEN after CLK

↑

Data high

0.5

0.5

CLKEN after CLK

↑

Data low

0.5

0.5

(unless otherwise noted) (see Figure 2)

SN54ALVTH16601

SN74ALVTH16601

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

150

150

MHz

t

Pulse duration

LE high

1.8

1.8

ns

tw

Pulse duration

CLK high or low

2.3

2.3

ns

A or B before CLK

↑

Data high

2.4

2.4

A or B before CLK

↑

Data low

3.8

3.8

t

Setup time

A or B before LE

↓

CLK high

1

1

ns

tsu

Setup time

A or B before LE

↓

CLK low

0.6

0.6

ns

CLKEN before CLK

↑

Data high

1.4

1.4

CLKEN before CLK

↑

Data low

1.9

1.9

A or B after CLK

↑

Data high

0.5

0.5

A or B after CLK

↑

Data low

0.5

0.5

th

Hold time

A or B after LE

↓

CLK high

2

2

ns

th

Hold time

A or B after LE

↓

CLK low

2.3

2.3

ns

CLKEN after CLK

↑

Data high

0.6

0.6

CLKEN after CLK

↑

Data low

0.5

0.5

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.