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DAC7621EB Datasheet(PDF) 9 Page - Texas Instruments |
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DAC7621EB Datasheet(HTML) 9 Page - Texas Instruments |
9 / 16 page ® 9 DAC7621 The digital data into the DAC7621 is double-buffered. This means that new data can be entered into the DAC without disturbing the old data and the analog output of the con- verter. At some point after the data has been entered into the serial shift register, this data can be transferred into the DAC register. This transfer is accomplished with a HIGH to LOW transition of the LOADDAC pin. However, the LOADDAC pin makes the DAC register transparent. If new data be- comes available on the bus register while LOADDAC is LOW, the DAC output voltage will change as the data changes. To prevent this, CS must be returned HIGH prior to changing data on the bus. At any time, the contents of the DAC register can be set to 000H (analog output equals 0V) by taking the CLR input LOW. The DAC register will remain at this value until CLR is returned HIGH and LOADDAC is taken LOW to allow the contents of the input register to be transferred to the DAC register. If LOADDAC is LOW when CLR is taken LOW, the DAC register will be set to 000H and the analog output driven to 0V. When CLR is returned HIGH, the DAC register and the analog output will respond accordingly. DIGITAL-TO-ANALOG CONVERTER The internal DAC section is a 12-bit voltage output device that swings between ground and the internal ref- erence voltage. The DAC is realized by a laser-trimmed R-2R ladder network which is switched by N-channel MOSFETs. The DAC output is internally connected to the rail-to-rail output operational amplifier. OPERATION The DAC7621 is a 12-bit digital-to-analog converter (DAC) complete with an input shift register, DAC register, laser- trimmed 12-bit DAC, on-board reference, and a rail-to-rail output amplifier. Figure 1 shows the basic operation of the DAC7621. INTERFACE Figure 1 shows the basic connection between a microcontroller and the DAC7621. The interface consists of a Read/Write (R/W), data, and a load DAC signal (LOADDAC). In addition, a chip select (CS) input is avail- able to enable the DAC7621 when there are multiple de- vices. The data format is Straight Binary. An asynchronous clear input (CLR) is provided to simplify start-up or periodic resets. Table I shows the relationship between input code and output voltage. DAC7621 Full-Scale Range = 4.095V Least Significant Bit = 1mV DIGITAL INPUT CODE ANALOG OUTPUT STRAIGHT OFFSET BINARY (V) DESCRIPTION FFFH +4.095 Full Scale 801H +2.049 Midscale + 1 LSB 800H +2.048 Midscale 7FFH +2.047 Midscale – 1 LSB 000H 0 Zero Scale TABLE I. Digital Input Code and Corresponding Ideal Analog Output. FIGURE 1. Basic Operation of the DAC7621. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CLR V DD V OUT AGND DGND DB11 DB10 DB9 DB8 DB7 LOADDAC CS R/W DB0 DB1 DB2 DB3 DB4 DB5 DB6 DAC7621E Load DAC Chip Select Read/Write 10 µF +5V Clear Data Bus Data Bus 0V to +4.095V 0.1 µF + |
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