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54ACT16823 Datasheet(PDF) 1 Page - Texas Instruments |
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54ACT16823 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 8 page 54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS160A – APRIL 1991 – REVISED APRIL 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Members of the Texas Instruments Widebus Family D Inputs Are TTL-Voltage Compatible D Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D EPIC (Enhanced-Performance Implanted CMOS) 1- µm Process D Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, parity bus interfacing, and working registers. The ’ACT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock. A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74ACT16823 is packaged in theTI shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16823 is characterized for operation over the full military temperature range of 55 °C to 125°C. The 74ACT16823 is characterized for operation from –40 °C to 85°C Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1CLR 1OE 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2OE 2CLR 1CLK 1CLKEN 1D1 GND 1D2 1D3 VCC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8 GND 2D9 2CLKEN 2CLK 54ACT16823 . . . WD PACKAGE 74ACT16823 . . . DL PACKAGE (TOP VIEW) |
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