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54AC11112 Datasheet(PDF) 1 Page - Texas Instruments

Part No. 54AC11112
Description  DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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54AC11112 Datasheet(HTML) 1 Page - Texas Instruments

   
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54AC11112, 74AC11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS073A – JUNE 1989 – REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
© 1993, Texas Instruments Incorporated
2–1
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC and GND Configuration
Minimizes High-Speed Switching Noise
EPIC ™ (Enhanced-Performance Implanted
CMOS) 1-
µm Process
500-mA Typical Latch-Up Immunity
at 125
°C
ESD Protection Exceeds 2000 V,
MIL STD-883C Method 3015
Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When preset and clear are inactive
(high), data at the J and K inputs meeting the setup
time requirements are transferred to the outputs
on the negative-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not
directly related to the fall time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by tying J and K high.
The 54AC11112 is characterized for operation over the full military temperature range of – 55
°C to 125°C. The
74AC11112 is characterized for operation from – 40
°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
LX
X
X
L
H
L
LX
X
X
H{
H{
H
H
LL
QO
QO
H
H
HL
H
L
H
H
LHL
H
H
H
H
H
Toggle
H
H
H
X
X
QO
QO
† This configuration is nonstable; that is, it will not persist
when either PRE or CLR returns to its inactive (high) level.
54AC11112 ...J PACKAGE
74AC11112 ...D OR N PACKAGE
(TOP VIEW)
54AC11112 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
2J
1J
1K
1CLK
1CLR
VCC
2CLR
2CLK
2K
3
2
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
2CLK
2K
NC
2J
2PRE
1K
1J
NC
1PRE
1Q
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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