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DP83256 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DP83256 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 144 page  TLF11708 PRELIMINARY October 1994 DP8325656-AP57 PLAYERa TM Device (FDDI Physical Layer Controller) General Description The DP8325656-AP57 Enhanced Physical Layer Control- ler (PLAYERa device) implements one complete Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T95 standard The PLAYERa device integrates state of the art digital clock recovery and improved clock generation functions to enhance performance eliminate external components and remove critical layout requirements FDDI Station Management (SMT) is aided by Link Error Monitoring support Noise Event Timer (TNE) support Op- tional Auto Scrubbing support an integrated configuration switch and built-in functionality designed to remove all strin- gent response time requirements such as PC React and CF React Features Y Single chip FDDI Physical Layer (PHY) solution Y Integrated Digital Clock Recovery Module provides en- hanced tracking and greater lock acquisition range Y Integrated Clock Generation Module provides all neces- sary clock signals for an FDDI system from an external 125 MHz reference Y Alternate PMD Interface (DP83256-AP57) supports UTP twisted pair FDDI PMDs with no external clock re- covery or clock generation functions required Y No External Filter Components Y Connection Management (CMT) Support (LEM TNE PC React CF React Auto Scrubbing) Y Full on-chip configuration switch Y Low Power CMOS-BIPOLAR design using a single 5V supply Y Full duplex operation with through parity Y Separate management interface (Control Bus) Y Selectable Parity on PHY-MAC Interface and Control Bus Interface Y Two levels of on-chip loopback Y 4B5B encoderdecoder Y Framing logic Y Elasticity Buffer Repeat Filter and Smoother Y Line state detectorgenerator Y Supports single attach stations dual attach stations and concentrators with no external logic Y DP83256 for SASDAS single path stations Y DP83257 for SASDAS singledual path stations Y DP83256-AP for SASDAS single path stations that re- quire the alternate PMD interface TLF11708 – 1 FIGURE 1-1 FDDI Chip Set Overview TRI-STATE is a registered trademark of National Semiconductor Corporation BMACTM BSITM CDDTM CDLTM CRDTM CYCLONETM MACSITM PLAYERTM PLAYERaTM and TWISTERTM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M115Printed in U S A |
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