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ADS8910B Datasheet(PDF) 33 Page - Texas Instruments |
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ADS8910B Datasheet(HTML) 33 Page - Texas Instruments |
33 / 68 page SCLK SDO-x Device Host Controller SCLK SDI tpcb_CK tpcb_SDO td_ISO td_ISO Digital Isolator (Optional) tsu_h td_ckdo td_delcap clk-SPI d_total-serial 1 f 2 t d u d_total_serial pcb_CK d_iso d_ckdo d_iso pcb_SDO su_h t t t t t t t SCLK SDO-x Device Host Controller SCLK SDI tpcb_CK tpcb_SDO td_ISO td_ISO Digital Isolator (Optional) tsu_h td_ckdo 33 ADS8910B ADS8912B ADS8914B www.ti.com SBAS707A – JUNE 2016 – REVISED JULY 2016 Product Folder Links: ADS8910B ADS8912B ADS8914B Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.5.4 Data Transfer Protocols This device family features a multiSPI digital interface that allows the host controller to operate at slower SCLK speeds and still achieve the required throughput and response time. The multiSPI digital interface module offers two options to reduce the SCLK speed required for data transfer: • Increase the width of the output data bus. • Enable double data rate (DDR) transfer. These two options can be combined to achieve further reduction in SCLK speed. Figure 44 shows the delays in the communication channel between the host controller and the device in a typical serial communication. Figure 44. Delays in Serial Communication For example, if tpcb_CK and tpcb_SDO are the delays introduced by the printed circuit board (PCB) traces for the serial clock and SDO signals, td_CKDO is the clock-to-data delay of the device, td_ISO is the propagation delay introduced by the digital isolator, and tsu_h is the setup time specification of the host controller, then the total delay in the path is given by Equation 11: (11) In a standard SPI protocol, the host controller and the device launch and capture data bits on alternate SCLK edges. Therefore, the td_total_serial delay must be kept to less than half of the SCLK duration. Equation 12 shows the fastest clock allowed by the SPI protocol: (12) Larger values of the td_total_serial delay restricts the maximum SCLK speed for the SPI protocol, resulting in higher read and response times, and can possibly limit the throughput. Figure 45 shows a delay (td_delcap) introduced in the capture path (inside the host controller). Figure 45. Delayed Capture |
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