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ADS1120QPWRQ1 Datasheet(PDF) 3 Page - Texas Instruments |
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ADS1120QPWRQ1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 67 page 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 CLK DGND AVSS AIN3/REFN1 AIN2 REFN0 REFP0 AIN1 AIN0/REFP1 AVDD DVDD DRDY DOUT/DRDY DIN SCLK CS ADS1120-Q1 www.ti.com SBAS683A – AUGUST 2014 – REVISED OCTOBER 2014 5 Pin Configurations and Functions PW Package TSSOP-16 (Top View) Pin Functions PIN NUMBER NAME TYPE DESCRIPTION 1 SCLK Digital input Serial clock input Chip select, active low. 2 CS Digital input Connect to DGND if not used. External clock source pin. 3 CLK Digital input Connect to DGND if not used. 4 DGND Digital Digital ground 5 AVSS Analog Negative analog power supply Analog input 3, negative reference input 1. 6 AIN3/REFN1 Analog input Internal low-side power switch connected between AIN3/REFN1 and AVSS. Leave unconnected or tie to AVDD if not used. Analog input 2. 7 AIN2 Analog input Leave unconnected or tie to AVDD if not used. Negative reference input 0. 8 REFN0 Analog input Leave unconnected or tie to AVDD if not used. Positive reference input 0. 9 REFP0 Analog input Leave unconnected or tie to AVDD if not used. Analog input 1. 10 AIN1 Analog input Leave unconnected or tie to AVDD if not used. Analog input 0, positive reference input 1. 11 AIN0/REFP1 Analog input Leave unconnected or tie to AVDD if not used. 12 AVDD Analog Positive analog power supply 13 DVDD Digital Positive digital power supply Data ready, active low. 14 DRDY Digital output Leave unconnected or tie to DVDD using a weak pull-up resistor if not used. 15 DOUT/DRDY Digital output Serial data output combined with data ready, active low 16 DIN Digital input Serial data input Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADS1120-Q1 |
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