ADS1120-Q1 datasheet(37/67 Pages) TI1

Part #	ADS1120-Q1

Description	Automotive, Low-Power, Low-Noise, 16-Bit, Analog-to-Digital Converter for Small-Signal Sensors

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CS

SCLK

DOUT/DRDY

DIN

Hi-Z

1

9

17

DATA MSB

DATA LSB

DRDY

Next Data Ready

25

ADS1120-Q1

www.ti.com

SBAS683A – AUGUST 2014 – REVISED OCTOBER 2014

8.5.6 Interfacing with Multiple Devices

When connecting multiple ADS1120-Q1 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely

shared by using a dedicated chip-select (CS) line for each SPI-enabled device. When CS transitions high for the

respective device, DOUT/DRDY enters a 3-state mode. Therefore, DOUT/DRDY cannot be used to indicate

when new data are available if CS is high, regardless of the DRDYM bit setting in the configuration register. Only

the dedicated DRDY pin indicates that new data are available, because the DRDY pin is actively driven even

when CS is high.

In some cases the DRDY pin cannot be interfaced to the microcontroller. This scenario can occur if there are

insufficient GPIO channels available on the microcontroller or if the serial interface must be galvanically isolated

and thus the amount of channels must be limited. Therefore, in order to evaluate when a new conversion of one

of the devices is ready, the microcontroller can periodically drop CS to the respective device and poll the state of

the DOUT/DRDY pin. When CS goes low, the DOUT/DRDY pin immediately drives either high or low, provided

that the DRDYM bit is configured to 1. If the DOUT/DRDY line drives low, when CS is taken low, new data are

currently available. If the DOUT/DRDY line drives high, no new data are available. This procedure requires that

DOUT/DRDY is high after reading each conversion result and before taking CS high. To make sure DOUT/DRDY

is taken high, send 16 additional SCLKs with DIN held low after each data read operation. DOUT/DRDY reads

low during the first eight SCLKs after the conversion result is read, and reads high during the following eight

SCLKs, as shown in Figure 67. Alternatively, valid data can be retrieved from the device at any time without

concern of data corruption by using the RDATA command.

Figure 67. Example of Taking DOUT/DRDY High After Reading a Conversion Result

8.6 Register Map

8.6.1 Configuration Registers

The device has four 8-bit configuration registers that are accessible through the serial interface using the RREG

and WREG commands. The configuration registers control how the device operates and can be changed at any

time without causing data corruption. After power-up or reset, all registers are set to the default values (which are

all 0). All registers retain their values during power-down mode. Table 11 shows the register map of the

configuration registers.

Table 11. Configuration Register Map

REGISTER

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(Hex)

00h

MUX[3:0]

GAIN[2:0]

PGA_BYPAS

S

01h

DR[2:0]

MODE[1:0]

CM

TS

BCS

02h

VREF[1:0]

50/60[1:0]

PSW

IDAC[2:0]

03h

I1MUX[2:0]

I2MUX[2:0]

DRDYM

RESERVED

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