ADC12081

SNAS020D – MARCH 2000 – REVISED MARCH 2013

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FUNCTIONAL DESCRIPTION

The ADC12081 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into

12-bit digital words at 5 megasamples per second (MSPS). This device utilizes a proprietary pipeline architecture

and algorithm to minimize die size and power consumption. The ADC12081 uses self-calibration and digital error

correction to maintain accuracy and performance over temperature. The ADC12081 has an input sample-and-

hold amplifier and internal reference buffer. The analog input and the reference voltage are converted to

differential signals for internal use. Using differential signals in the analog conversion core reduces crosstalk and

noise pickup from the digital section and power supply.

The pipeline conversion core has 15 sequential signal processing stages. Each stage receives an analog signal

from the previous stage (called “residue” ) and produces a 1-bit digital output that is sent to the digital correction

module. At each stage the analog signal received from the previous stage is compared to an internally generated

reference level. It is then amplified by a factor of 2, and, depending on the output of the comparator, the internal

reference signal may be subtracted from the amplifier output. This produces the residue that is passed to the

next stage.

The calibration module is activated at power-on or by user request. During calibration the conversion core is put

into a special mode of operation in order to determine inherent errors in the analog conversion blocks and to

determine correction coefficients for each digital output bit from the conversion core and stores these coefficients

in RAM. The digital correction module uses the coefficients in RAM to convert the raw data bits from the

conversion core into the 12-bit digital output code.

Applications Information

ANALOG INPUTS

Reference Input

to a clean, quiet point in analog ground.

Analog Signal Input

quiet point in analog ground.

DIGITAL INPUTS

The ADC12081 has four digital inputs. They are CLOCK, CAL, OE and PD.

CLOCK

The CLOCK signal drives an internal phase delay loop to create timing for the ADC. The clock input should be

driven with a stable, low phase jitter TTL level clock signal in the range of 0.5 to 5 MHz. The trace carrying the

clock signal should be as short as possible. This trace should not cross any other signal line, analog or digital,

not even at 90°. A 100 Ohm resistor should be placed in series with the CLOCK pin, as close to the pin as

possible.

CAL

The level sensitive CAL input must be pulsed high for at least three clock cycles to begin ADC calibration. For

best performance, calibration should be performed about ten seconds after power up, after resetting the ADC,

and after the temperature has changed by more than 50°C since the last calibration was performed.

Calibration should be performed at the same clock frequency that the ADC12081 will be used for conversions to

minimize offset errors. Calibration takes 4000 clock cycles. Irrelevant data may appear during CAL.

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