ADC12081 datasheet(7/25 Pages) TI1

Part #	ADC12081

Description	12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold

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Manufacturer	TI1 [Texas Instruments]

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ADC12081

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SNAS020D – MARCH 2000 – REVISED MARCH 2013

DC and Logic Electrical Characteristics

The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,

fCLK = 50MHz, CL = 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA = TMIN to TMAX; all other limits TA

= TJ = 25°C

(1) (2) (3)

Units

Symbol

Parameter

Conditions

Typical(4)

Limits(5)

(Limits)

CLK, OE Digital Input Characteristics

VIH

Logical "1" Input Voltage

V+ = 5.25V

2.0

V(min)

VIL

Logical "0" Input Voltage

V+ = 4.75V

0.8

V(min)

IIH

Logical "1" Input Current

VIN = 5.0V

5

µA

IIL

Logical "0" Input Current

VIN = 0V

−5

µA

CIN

VIN Input Capacitance

8

pF

D0 - D11 Digital Output Characteristics(6)

VOH

Logical "1" Output Voltage

IOUT = −1mA

4

V (min)

VOL

Logical "0" Output Voltage

IOUT = 1.6mA

0.4

V (max)

IOZ

TRI-STATE Output Current

VOUT = 3V or 5V

10

µA

VOUT = 0V

−10

µA

+ISC

Output Short Circuit Source Current

VDDO= 3V, VOUT = 0V

−14

mA(min)

−ISC

Output Short Circuit Sink Current

VDDO= 3V, VOUT = VO

16

mA(min)

Power Supply Characteristics

PD = VDDO

2.5

4

mA(max)

IA

Analog Supply Current

PD = DGND

20

26

mA(max)

PD = VDDO

0.5

2

mA(max)

ID

Digital Supply Current

PD = DGND

1

2

mA(max)

PD = VDDO

15

30

mW(max)

Total Power Consumption

PD = DGND

105

140

mW(max)

(1)

The inputs are protected as shown below. Input voltage magnitudes up to 5V above VA or to 5V below GND will not damage this device,

provided current is limited per Note 3. However, errors in the A/D conversion can occur if the input goes above VA or below GND by

more than 100 mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate conversions.

(2)

To guarantee accuracy, it is required that |VA - VD| ≤ 100mV and separate bypassed capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +2.0V, the 12-bit LSB is 488µV.

(4)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms.

(5)

Tested limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).

(6)

Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output

voltage is forced to 1.4V.

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