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ADC32RF45 Datasheet(PDF) 82 Page - Texas Instruments |
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ADC32RF45 Datasheet(HTML) 82 Page - Texas Instruments |
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82 / 108 page  82 ADC32RF45 SBAS747B – MAY 2016 – REVISED JULY 2016 www.ti.com Product Folder Links: ADC32RF45 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.5.8.22 Register 037h (address = 037h), Decimation Filter Page Figure 125. Register 037h 7 6 5 4 3 2 1 0 0 0 0 0 TEST PATTERN SEL W-0h W-0h W-0h W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 81. Register 037h Field Descriptions Bit Field Type Reset Description 7-3 0 W 0h Must write 0 3-0 TEST PATTERN SEL R/W 0h These bits select the test pattern output on the channel. 0000 = Normal operation using ADC output data 0001 = Outputs all 0s 0010 = Outputs all 1s 0011 = Outputs toggle pattern: output data are an alternating sequence of 10101010101010 and 01010101010101 0100 = Output digital ramp: output data increment by one LSB every clock cycle from code 0 to 16384 0110 = Single pattern: output data are custom pattern 1 (75h and 76h) 0111 = Double pattern: output data alternate between custom pattern 1 and custom pattern 2 1000 = Deskew pattern: output data are AAAAh 1001 = SYNC pattern: output data are FFFFh 8.5.8.23 Register 03Ah (address = 03Ah), Decimation Filter Page Figure 126. Register 03Ah 7 6 5 4 3 2 1 0 0 0 0 0 0 0 TEST PAT RES TP RES EN W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 82. Register 03Ah Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1 TEST PAT RES R/W 0h Pulsing this bit resets the test pattern. The test pattern reset must be enabled first (bit D0). 0 = Normal operation 1 = Reset the test pattern 0 TP RES EN R/W 0h This bit enables the test pattern reset. 0 = Reset disabled 1 = Reset enabled |
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