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ADC16DX370RMET Datasheet(PDF) 55 Page - Texas Instruments |
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ADC16DX370RMET Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 77 page  ADC16DX370 www.ti.com SNVSA18C – APRIL 2014 – REVISED AUGUST 2014 TI recommends gapped-periodic or one-shot signals for most applications because the SYSREF signal is not active during normal sampling operation. Periodic signals that toggle constantly introduce spurs into the signal spectrum that degrade the sensitivity of the system. 9.1.2.5 SYSREF Timing The SYSREF timing requirements depend on whether deterministic latency of the JESD204B link is required. If deterministic latency is required, then the SYSREF signal must meet setup and hold requirements relative to the CLKIN signal. In the case that the internal CLKIN divider is used and a very high-speed signal is provided to the CLKIN input, the SYSREF signal must meet setup and hold requirements relative to the very high-speed signal at the CLKIN input. If deterministic latency is not required, then the SYSREF signal may be supplied as an asynchronous signal (possibly achieving < ± 2 frame clock cycles latency variation) or not provided at all (resulting in latency variation as large as the multi-frame period). 9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features Selecting the proper settings for the SYSREF offset feature depends on the condition of SYSREF in the idle state and the type of SYSREF signal being transmitted. Table 29 describes the possible SYSREF idle cases and the corresponding SYSREF offset to apply. TI recommends the use of the SYSREF detection gate for most applications. The gate is enabled when SYSREF is being transmitted and the gate is disabled before the SYSREF transmitter is put in the idle state. Although the SYSREF offset feature does not support situations where the SYSREF transmitter is in a 0 V or Hi-Z common- mode condition during the idle state, the SYSREF gate can be used to ignore the SYSREF input during those conditions. In those cases, time is required to dissipate the voltage build-up on the AC coupling capacitors when the SYSREF returns to an active state. Enabling the SYSREF gate immediately sends a logic signal to a logic block responsible for aligning the internal frame clock and LMFC. If the signal at the SYSREF input is logic high when the gate is enabled, then a "false" rising edge event causes a re-alignment of the internal clocks, despite the fact that the event is not an actual SYSREF rising edge. The SYSREF rising edge following the gate enable then causes a subsequent re-alignment with the desired alignment. TI highly recommends the SYSREF clocking schemes described in Table 30. Table 29. SYSREF Offset Feature Usage Cases SYSREF SYSREF Idle SYSREF Idle Common-Mode (VIS) at the SYSREF Signal Type VOD at TX Transmitter Offset Feature Setting Periodic N/A N/A 0 mV = 0 VIS same during idle and non-idle states 0 mV Gapped-periodic or > 0 (logic high) VIS same during idle and non-idle states 400 mV One-shot < 0 (logic low) VIS same during idle and non-idle states –400 mV 0 0 SYSREF offset feature does not Any support these cases Hi-Z Hi-Z Table 30. Recommended SYSREF Clocking Schemes SYSREF at TX During Idle SYSREF Rx Offset Coupling SYSREF Type SYSREF Detection Gate State Setting One-shot or gapped- VOD logic low, VIS does not Disabled during SYSREF idle, AC Coupled –400 mV at all times periodic(1) change during idle enabled during LMFC alignment VOD either logic state, VIS Disabled during SYSREF idle, DC Coupled One-shot or gapped-periodic 0 mV at all times does not change during idle enabled during LMFC alignment (1) A gapped-periodic signal used in this recommended clocking scheme must have a pulse train duration of less than the RC time constant where R = 50 Ω and C is the value of the AC coupling capacitor. Using a 0.1-µF capacitor, the pulse train should be less than 5 µs. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 55 Product Folder Links: ADC16DX370 |
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