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ADC16DX370RMER Datasheet(PDF) 56 Page - Texas Instruments |
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ADC16DX370RMER Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 77 page  0.01uF 100:-diff Serial Lane Transmitter Serial Lane Receiver 100: PCB Channel 1k: 50: 50: 3pF 2k: 1k: 2k: 2.5V 34k: 34k: 100:-diff SYNCb Receiver SYNCb Transmitter PCB Channel ADC16DX370 SNVSA18C – APRIL 2014 – REVISED AUGUST 2014 www.ti.com 9.1.2.7 Driving the SYNCb Input The SYNCb input is part of the JESD204B interface and is used to send synchronization requests from the serial data receiver to the transmitter, the ADC16DX370 device. The SYNCb signal, quantified as the (SYNCb+ – SYNCb–), is a differential active low signal. In the case of the ADC16DX370 device, a JESD204B subclass 1 device, a SYNCb assertion (logic low) indicates a request for synchronization by the receiver. The SYNCb input is a differential receiver as shown in Figure 51. Resistors provide an internal 100- Ω differential termination as well as a voltage divider circuit that gives the SYNCb receiver a wide input common-mode range. The SYNCb signal must be DC coupled from the driver to the SYNCb inputs; therefore, the wide common-mode range allows the use of many different logic standards including LVDS and LVPECL. No additional external components are needed for the SYNCb signal path as shown in the interface circuit of Figure 51, but providing an electrical probing site is recommended for system debug. Figure 51. SYNCb Input Receiver and Interface The SYNCb input is an asynchronous input and does not have sub-clock-cycle setup and hold requirements relative to the CLKIN or any other input to the ADC16DX370 device. The SYNCb input also does not have setup and hold requirements relative to the frame and LMFC system clocks unless the delay through the JESD204B link is longer than a multi-frame. A design that has link delay greater than a multi-frame does not strictly follow the standard rules for achieving deterministic latency, but may be required in many applications and may still achieve deterministic latency. In this case, it is important to de-assert SYNCb within the window of the desired multi-frame period. 9.1.3 Output Serial Interface Considerations 9.1.3.1 Output Serial-Lane Interface The output high speed serial lanes must be AC coupled to the receiving device with 0.01-µF capacitors as shown in Figure 52. DC coupling to the receiving device is not supported. The lane channel on the PCB must be a 100- Ω differential transmission line with dominant coupling between the differential traces instead of to adjacent layers. The lane must terminate at a 100- Ω termination inside the receiving device. Avoid changing the direction of the channel traces abruptly at angles larger than 45°. Figure 52. High-Speed Serial-Lane Interface The recommended spacing between serial lanes is 3× the differential line spacing or greater. High speed serial lanes should be routed on top of or below adjacent, quiet ground planes to provide shielding. TI recommends that other high speed signal traces do not cross the serial lanes on adjacent PCB layers. If absolutely necessary, crossing should occur at a 90° angle with the trajectory of the serial lane to minimize coupling. 56 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADC16DX370 |
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