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ADC16DX370RMER Datasheet(PDF) 31 Page - Texas Instruments

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Part # ADC16DX370RMER
Description  ADC16DX370 Dual 16-Bit 370 MSPS ADC
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC16DX370RMER Datasheet(HTML) 31 Page - Texas Instruments

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Octet 0
(MSB)
(LSB)
Octet 1
(MSB)
(LSB)
D[15:0] = 16-bit Word
Octet 0
(MSB)
(LSB)
D[15:0] = 16-bit Word
Lane 0
Lane 0
Lane 1
D[15] D[14]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[0]
D[1]
D[2]
D[3]
D[4]
D[15] D[14]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[5]
D[6]
D[7]
D[0]
D[1]
D[2]
D[3]
D[4]
L=2
S=1
F=1
N=16
CS=0
1¶=16
L=1
S=1
F=2
N=16
CS=0
1¶=16
ADC16DX370
www.ti.com
SNVSA18C – APRIL 2014 – REVISED AUGUST 2014
Figure 33. Transport Layer Definitions for the Supported-Lane Configurations
8.3.11.3 ILA Information
Table 4 summarizes the information transmitted during the initial lane alignment (ILA) sequence. Mapping of
these parameters into the data stream is described in the JESD204B standard.
Table 4. Configuration of the JESD204B Serial-Data Receiver
Value
Parameter
Description
Single Lane Mode
Dual Lane Mode
ADJCNT
DAC LMFC adjustment
0
0
ADJDIR
DAC LMFC adjustment direction
0
0
BID
Bank ID
0
0
CF
Number of control words per frame clock period per link
0
0
CS
Number of control bits per sample
0
0
DID
Device identification number
0
0
F
Number of octets per frame (per lane)(1)
2
1
HD
High-density format
0
1
JESDV
JESD204 version
1
1
K
Number of frames per multi-frame(1)
Set by register as 9 to 32
Set by register as 17 to 32
L
Number of lanes per link(1)
1
2
LID
Lane identification number
0
0 (lane 0), 1 (lane 1)
M
Number of converters per device(1)
1
1
N
Converter resolution (1)
16
16
N’
Total number of bits per sample(1)
16
16
PHADJ
Phase adjustment request to DAC
0
0
S
Number of samples per converter per frame cycle(1)
1
1
Set by register as 0 (disabled)
Set by register as 0
SCR
Scrambling enabled
or 1
(disabled) or 1
SUBCLASSV Device subclass version
1
1
RES1
Reserved field 1
0
0
RES2
Reserved field 2
0
0
(1)
These parameters have a binary-value-minus-1 encoding applied before being mapped into the link configuration octets. For example, F
= 2 is encoded as 1, and F = 1 is encoded as 0.
Copyright © 2014, Texas Instruments Incorporated
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