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ADC16DX370 Datasheet(PDF) 5 Page - Texas Instruments |
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ADC16DX370 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 77 page  AGND VA3.0 + - SYSREF+ SYSREF- 1k: 0.5V 1k: 10k: AGND VA1.2 AGND VA3.0 SYNC+ 50: 50: SYNC- 1k: 2.5V AGND 2k: 2k: 34k: 34k: 3pF 1k: 2.5V VA3.0 + - SDO 80: 80: VA3.0 VA1.2 ADC16DX370 www.ti.com SNVSA18C – APRIL 2014 – REVISED AUGUST 2014 Pin Functions (continued) PIN TYPE OR DIAGRAM DESCRIPTION NAME NUMBER SPI serial clock pin Serial data is shifted into and out of the device SCLK 53 synchronous with this clock signal. Compatible with 1.2- to 3.0-V CMOS logic levels. SPI data input pin Serial data is shifted into the device on this pin while SDI 47 the CSB signal is asserted. Compatible with 1.2- to 3.0-V CMOS logic levels. SPI data output pin Serial data is shifted out of the device on this pin during a read command while CSB is asserted. The SDO 48 output logic level is configurable as 1.2, 1.8, 2.5, or 3.0 V. The output level must be configured after power up and before performing a read command. See the Register Descriptions for configuration details. Differential SYNCb signal input pins DC coupling is required for coupling the SYNCb signal to these pins. Each pin is internally terminated to the DC bias with a large resistor. An internal 100- Ω differential termination is provided therefore an external SYNCb+, SYNCb– 27, 28 termination is not required. Additional resistive components in the input structure give the SYNCb input a wide input common-mode range. The SYNCb signal is active low and therefore asserted when the voltage at SYNCb+ is less than at SYNCb–. Differential SYSREF signal input pins Each pin is internally terminated to a DC bias with a 1- k Ω resistor. An external 100-Ω differential termination must always be provided. AC coupling using capacitors SYSREF+, 23, 24 is required for coupling the SYSREF signal to these SYSREF– pins if the clock driver cannot meet the common-mode requirements. In the case of AC coupling, the termination must be placed on the source side of the coupling capacitors. 1.2-V analog power supply pins These pins must be connected to a quiet source and VA1.2 8, 21, 30, 50 Supply input pin decoupled to AGND with a 0.1- μF and 0.01-μF capacitor located close to each pin. 1.8-V analog power supply pins 7, 15, 20, 29, These pins must be connected to a quiet source and VA1.8 Supply input pin 51, 56 decoupled to AGND with a 0.1- μF and 0.01-μF capacitor located close to each pin. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC16DX370 |
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