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ADC16DX370 Datasheet(PDF) 30 Page - Texas Instruments |
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ADC16DX370 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 77 page  ADC16DX370 SNVSA18C – APRIL 2014 – REVISED AUGUST 2014 www.ti.com 8.3.9 Data Format Data may be output in the serial stream as 2’s complement format by default or optionally as offset binary. This formatting is configured through the SPI and is performed in the data path prior to JESD204B data framing and 8b/10b encoding. 8.3.10 JESD204B Supported Features The ADC16DX370 device supports a feature set of the JESD204B standard targeted to its intended applications but does not implement all the flexibility of the standard. Table 3 summarizes the level of feature support. Table 3. ADC16DX370 Feature Support for the JESD204B Serial Interface Feature Supported Not Supported Subclass • Subclass 1, 0(1) • Subclass 2 • AC coupled CLKIN and SYSREF Device Clock (CLKIN) and • DC coupled CLKIN and SYSREF (special cases) SYSREF • Periodic, Pulsed Periodic and One-Shot SYSREF • Deterministic latency supported for subclass 1 • Deterministic latency not supported for non- Latency implementations using standard SYSREF signal standard implementations Electrical layer • LV-OIF-11G-SR interface and performance • TX lane polarity inversion features • AC coupled serial lanes • DC coupled serial lanes • F, S, and HD configuration depends on L and is not independently configurable • L = 1 or 2 for each channel Transport layer • M, N, N’, CS, CF configuration features and • K configuration configuration • Idle link mode • Scrambling • Short and Long transport layer test patterns • 8b/10b encoding Data link layer • Lane synchronization • RPAT/JSPAT test sequences features • D21.5, K28.5, ILA, PRBS7, PRBS23, Ramp test sequences (1) The ADC16DX370 supports most subclass 0 requirements, but is not strictly subclass compliant. 8.3.11 Transport Layer Configuration The transport layer features supported by the ADC16DX370 device are a subset of possible features described in the JESD204B standard. The configuration options are intentionally simplified to provide the lowest power and most easy-to-use solution. 8.3.11.1 Lane Configuration Each channel outputs its digital data on up to two serial lanes that support JESD204B. The number of transmission lanes per channel (L) is configurable as 1 or 2. The device does not allow transmitting both channels on the same lane. When using one serial lane per channel, the serial-data lane transmits at 20 times the sampling rate. A 370 MSPS sampling rate corresponds to a 7.4 Gb/s per lane rate. When using two serial lanes per channel, the serial data rate is 10 times the sampling rate. A 370 MSPS sampling rate corresponds to a 3.7 Gb/s per lane rate. 8.3.11.2 Frame Format The format of the data arranged in a frame depends on the L setting. The octets per frame (F), samples per frame (S), and high-density mode (HD) parameters are not independently configurable. The N, N’, CS, CF, M, and HD parameters are fixed and not configurable. Figure 33 shows the data format for L = 1 and L = 2. M = 1 in this device, indicating one converter per device and each channel is considered a different device. Therefore, the L value corresponds to the number of lanes used by a channel, not the number of lanes output from the chip. 30 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADC16DX370 |
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