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ADC14155 Datasheet(PDF) 4 Page - Texas Instruments |
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ADC14155 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 28 page  DRGND VDR DGND VA AGND VA AGND VA ADC14155 SNAS350I – APRIL 2006 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol Equivalent Circuit Description DIGITAL I/O 11 CLK+ The clock input pins can be configured to accept either a single- ended or a differential clock input signal. When the single-ended clock mode is selected through CLK_SEL/DF (pin 8), connect the clock input signal to the CLK+ pin and connect the CLK − pin to AGND. When the differential clock mode is selected through CLK_SEL/DF (pin 8), connect the positive and negative clock inputs to the CLK+ and CLK − pins, respectively. 12 CLK − The analog input is sampled on the falling edge of the clock input. This is a four-state pin controlling the input clock mode and output data format. CLK_SEL/DF = VA, CLK+ and CLK− are configured as a differential clock input. The output data format is 2's complement. CLK_SEL/DF = (2/3)*VA, CLK+ and CLK− are configured as a differential clock input. The output data format is offset binary. 8 CLK_SEL/DF CLK_SEL/DF = (1/3)*VA, CLK+ is configured as a single-ended clock input and CLK − should be tied to AGND. The output data format is 2's complement. CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock input and CLK − should be tied to AGND. The output data format is offset binary. This is a two-state input controlling Power Down. PD = VA, Power Down is enabled. In the Power Down state only the 7 PD reference voltage circuitry remains active and power dissipation is reduced. PD = AGND, Normal operation. Digital data output pins that make up the 14-bit conversion result. D0 17-24, D0–D13 (pin 17) is the LSB, while D13 (pin 32) is the MSB of the output 27-32 word. Output levels are CMOS compatible. Over-Range Indicator. This output is set HIGH when the input 33 OVR amplitude exceeds the 14-bit conversion range (0 to 16383). Data Ready Strobe. This pin is used to clock the output data. It has the same frequency as the sampling clock. One word of data is output in each cycle of this signal. The rising edge of this signal 34 DRDY should be used to capture the output data. ANALOG POWER Positive analog supply pins. These pins should be connected to a 1, 6, 9, 37, VA quiet +3.3V source and be bypassed to AGND with 100 pF and 0.1 40, 41, 48 µF capacitors located close to the power pins. 2, 5, 10, 38, The ground return for the analog supply. 39, 42, 47, AGND Note: Exposed pad on bottom of package must be soldered to Exposed Pad ground plane to ensure rated performance. 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC14155 |
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