74AC11194

4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

SCAS093 − NOVEMBER 1989 − REVISED APRIL 1993

2

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Function Table

INPUTS

OUTPUTS

CLEAR

MODE

CLOCK

SERIAL

PARALLEL

QA

QB

QC

QD

CLEAR

S1

S0

CLOCK

LEFT

RIGHT

A

B

C

D

QA

QB

QC

QD

L

X

X

X

X

X

X

X

X

X

L

L

L

L

H

X

XL

X

XX

XXX

QA0

QB0

QC0

QD0

H

H

H

↑

X

Xa

bc

d

a

bc

d

H

L

H

↑

X

HX

XXX

H

QAn

QBn

QCn

H

L

H

↑

X

LX

XXX

L

QAn

QBn

QCn

H

H

L

↑

H

XX

XXX

QBn

QCn

QDn

H

H

H

L

↑

L

XX

XXX

QBn

QCn

QDn

L

H

L

L

X

X

X

X

X

X

X

QAO

QBO

QCO

QDO

H = high level (steady state)

L = low level (steady state)

X = irrelevant (any input, including transitions)

↑ = transition from low to high level

a,b,c,d = the level of steady-state input at inputs A, B, C, or D, respectively.

QAO, QBO, QCO, QDO = the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were

established.

QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD respectively, before the most-recent ↑ transition of the clock.

timing clear, load, right-shift, inhibit, and clear sequences

CLK

S0

CLR

Load

Shift Right

Mode

Control

Inputs

S1

R

Serial

Data

Inputs

L

A

Parallel

Data

Inputs

B

H

L

C

D

H

L

Outputs

CLR

Shift Left

Inhibit

CLR