IDT72V201L15PFI datasheet(9/14 Pages) IDT

Part #	IDT72V201L15PFI

Description	3.3 VOLT CMOS SyncFIFO??256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tDS

D0 (First Valid Write)

tSKEW1

D0

D1

D3

D2

D1

tENS

tFRL

(1)

tREF

tA

tOLZ

tOE

tA

WCLK

D0 - D8

WEN2

(If Applicable)

RCLK

EF

REN1,

REN2

Q0 - Q8

OE

WEN1

4092 drw09

tENS

NOTE:

1.

When tSKEW1

≥ minimum specification, tFRL = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (

EF = LOW).

Figure 7. First Data Word Latency Timing

tENH

tENS

NO OPERATION

tOLZ

VALID DATA

tSKEW1

(1)

tCLK

tCLKH

tCLKL

tREF

tA

tOE

tOHZ

RCLK

REN1,

REN2

EF

Q0 - Q8

OE

WCLK

WEN1

WEN2

4092 drw08

NOTE:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for

EF to change during the current clock cycle. If the time between

the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then

EF may not change state until the next RCLK edge.

Figure 6. Read Cycle Timing

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IDT72V201L15PFI Datasheet(PDF) 9 Page - Integrated Device Technology

IDT72V201L15PFI Datasheet(HTML) 9 Page - Integrated Device Technology

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