PC33889

24

PC33889

By setting CEXT to 1 the transceiver cell supports sub bus communication.

note: if DFIS bit is set to 1, WUR register must be read before going into sleep or stop mode in order to clear the wake up flag.

During read out L0 must be at high level and should stay high when entering sleep or stop.

Status bits

comments:

CS2 bit at 0 = open failure. CS2 bit at 1 = short failure.

(CS3 bit at 0 and (CS1 = 1 or CS2 =1)) = CANH failure. CS3 bit at 1 = CANL failure.

CS1 and CS0 bits: short type failure coding (gnd, Vdd or Vbat).

In case of multiple failures, the last failure is reported.

7.2.4

IOR register

Some description.

CEXT

CCTR1

CCTR0

Mode

1

0

0

TermVBAT

10

1

TermVDD

11

0

RxOnly

11

1

RxTx

Table 7-6.

FDIS

L0 wake input filter (20us typical)

0

Enable (LO wake threshold selectable by WUR register)

1

Disable (L0 wake up threshold is low level only, no matter D0 and D1 bits set in WUR register).

CS3

CS2

CS1

CS0

Bus failure #

Description

0

0

0

0

no failure

0

0

0

1

1

CANH open wire

010

1

5

CANH short circuit to

ground

011

0

8, 3a

VDD

0

1

1

1

3

VBAT

1

0

0

1

2

CANL open wire

110

1

4, 7

CANL short circuit to

ground / CANL

111

0

9

VDD

1

1

1

1

6

VBAT

IOR

D3D2D1D0

$011b

W

HS1ON

GSLR1

GSLR0

R

SHIFT

HS1OT

V2LOW

VSUPLOW

Reset

00

0

Reset condition

POR, RESET

POR, RESET

POR, RESET

Table 7-7.

Freescale Semiconductor, Inc.

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