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DM54L73 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. DM54L73
Description  Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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DM54L73 Datasheet(HTML) 3 Page - National Semiconductor (TI)

   
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Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
VOH
High Level Output
VCC e Min IOH e Max
24
33
V
Voltage
VIL e Max VIH e Min
VOL
Low Level Voltage
VCC e Min IOL e Max
015
03
V
Voltage
VIL e Max VIH e Min
II
Input Current
Max
VCC e Max
J K
100
Input Voltage
VI e 55V
Clear
200
m
A
Clock
200
IIH
High Level Input
VCC e Max
J K
10
Current
VI e 24V
Clear
20
m
A
Clock
b
200
IIL
Low Level Input
VCC e Max
J K
b
018
Current
VI e 03V
Clear
b
036
mA
Clock
b
036
IOS
Short Circuit
VCC e Max
b
3
b
15
mA
Output Current
ICC
Supply Current
VCC e Max (Note 2)
15
288
mA
Note 1
All typicals are at VCC e 5V TA e 25 C
Note 2
With all outputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock is grounded
Switching Characteristics VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
RL e 4kX CL e 50 pF
Units
To (Output)
Min
Max
fMAX
Maximum Clock Frequency
6
MHz
tPHL
Propagation Delay Time
Clear to Q
150
ns
High to Low Level Output
tPLH
Propagation Delay Time
Clear to Q
75
ns
Low to High Level Output
tPLH
Propagation Delay Time
Clock to Q or Q
10
75
ns
Low to High Level Output
tPHL
Propagation Delay Time
Clock to Q or Q
10
150
ns
High to Low Level Output
3


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