CY7C346
USE ULTRA37000TM FOR
ALL NEW DESIGNS
Document #: 38-03005 Rev. *B
Page 7 of 21
Commercial and Industrial External Synchronous Switching Characteristics[6] Over Operating Range
Parameter
Description
7C346-25
7C346-30
7C346-35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tPD1
Dedicated Input to Combinatorial Output Delay[7]
25
30
35
ns
tPD2
I/O Input to Combinatorial Output Delay[10]
40
45
55
ns
tPD3
Dedicated Input to Combinatorial Output Delay with Expander
Delay[11]
37
44
55
ns
tPD4
I/O Input to Combinatorial Output Delay with Expander
Delay[4, 12]
52
59
75
ns
tEA
Input to Output Enable Delay[4, 7]
25
30
35
ns
tER
Input to Output Disable Delay[4, 7]
25
30
35
ns
tCO1
Synchronous Clock Input to Output Delay
14
16
20
ns
tCO2
Synchronous Clock to Local Feedback to Combinatorial
Output[4, 13]
30
35
42
ns
tS1
Dedicated Input or Feedback Set-Up Time to Synchronous
Clock Input[7, 14]
15
20
25
ns
tS2
I/O Input Set-Up Time to Synchronous Clock Input[7]
30
36
45
ns
tH
Input Hold Time from Synchronous Clock Input[7]
0
0
0
ns
tWH
Synchronous Clock Input HIGH Time
8
10
12.5
ns
tWL
Synchronous Clock Input LOW Time
8
10
12.5
ns
tRW
Asynchronous Clear Width[4, 7]
25
30
35
ns
tRR
Asynchronous Clear Recovery Time[4, 7]
25
30
35
ns
tRO
Asynchronous Clear to Registered Output Delay[7]
25
30
35
ns
tPW
Asynchronous Preset Width[4, 7]
25
30
35
ns
tPR
Asynchronous Preset Recovery Time[4, 7]
25
30
35
ns
tPO
Asynchronous Preset to Registered Output Delay[7]
25
30
35
ns
tCF
Synchronous Clock to Local Feedback Input[4, 15]
3
3
6
ns
tP
External Synchronous Clock Period (1/(fMAX3)
[4]
16
20
25
ns
fMAX1
External Feedback Maximum Frequency (1/(tCO1 + tS1))
[4, 16]
34.5
27.7
22.2
MHz
fMAX2
Internal Local Feedback Maximum Frequency, lesser of
(1/(tS1 + tCF)) or (1/tCO1)
[4, 17]
55.5
43.4
32.2
MHz
fMAX3
Data Path Maximum Frequency, lesser of (1/(tWL + tWH)),
(1/(tS1 + tH)) or (1/tCO1)
[4, 18]
62.5
50
40
MHz
fMAX4
Maximum Register Toggle Frequency (1/(tWL + tWH)
[4, 19]
62.5
50
40
MHz
tOH
Output Data Stable Time from Synchronous Clock Input[4, 20]
3
3
3
ns
Notes:
7. This specification is a measure of the delay from input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial
output on any output pin. This delay assumes no expander terms are used to form the logic function.
8. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset)
is applied to a dedicated input only and no signal path (either clock or data) employs expander logic.
9. If an input signal is applied to an I/O pin an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used,
add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders.
10. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
11. This specification is a measure of the delay from an input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 36, 66, or 68) to combinatorial
output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass
through the expander logic.
12. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to
form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
13. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array
and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This
parameter is tested periodically by sampling production material.
14. If data is applied to an I/O input for capture by a macrocell register, the I/O pin input set-up time minimums should be observed. These parameters are tS2 for
synchronous operation and tAS2 for asynchronous operation.
15. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array
input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for
feedback within the same LAB. This parameter is tested periodically by sampling production material.
16. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can
operate. It is assumed that all data inputs and external feedback signals are applied to dedicated inputs.
17. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must
also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local originating
within the same LAB.
18. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data
input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate tS for calculation.
19. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a clock
signal applied to the dedicated clock input pin.
20. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.This
specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic
array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The
clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
