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IDT72V201 Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT72V201
Description  3.3 VOLT CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V201 Datasheet(HTML) 2 Page - Integrated Device Technology

 
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IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Symbol
Name
I/O
Description
D0-D8
Data Inputs
I
Data inputs for a 9-bit bus.
RS
Reset
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF
and PAF go HIGH, and PAE and EF go LOW. A Reset is required before an initial Write after power-up.
WCLK
WriteClock
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
WEN1
Write Enable 1
I
If the FIFO is configured to have programmable flags, WEN1 is the only Write Enable pin. When WEN1 is
LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to
have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if the FF is LOW.
WEN2/LD
Write Enable 2/
I
The FIFO is configured at Reset to have either two write enables or programmable flags. If WEN2/LD
Load
is HIGH at Reset, this pin operates as a second write enable. If WEN2/LD is LOW at Reset, this pin operates
as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write
enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written
into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to
write or read the programmable flag offsets.
Q0-Q8
DataOutputs
O
Data outputs for a 9-bit bus.
RCLK
Read Clock
I
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
REN1
Read Enable 1
I
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data
will not be read from the FIFO if the EF is LOW.
REN2
Read Enable 2
I
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
OE
OutputEnable
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is
HIGH, the FIFO is not empty. EF is synchronized to RCLK.
PAE
Programmable
O
When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
Almost-EmptyFlag
offset at reset is Empty+7. PAE is synchronized to RCLK.
PAF
Programmable
O
When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default
Almost-FullFlag
offset at reset is Full-7. PAF is synchronized to WCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
is not full. FF is synchronized to WCLK.
VCC
Power
One 3.3V volt power supply pin.
GND
Ground
One 0 volt ground pin.
TQFP (PR32-1, order code: PF)
TOP VIEW
PLCC (J32-1, order code: J)
TOP VIEW
PIN CONFIGURATION
WEN1
WCLK
WEN2/
LD
V
Q8
Q7
Q6
Q5
5
6
7
8
16
CC
D1
PAF
PAE
GND
REN1
RCLK
REN2
D0
27 26 25
24
23
22
21
29 28
32 31 30
9 1011 1213 1415
4092 drw02
1
2
3
4
20
19
18
17
INDEX
RS
WEN1
WCLK
WEN2/
LD
VCC
Q8
Q7
Q6
Q5
5
6
7
8
9
10
11
12
13
D1
PAF
PAE
GND
REN1
RCLK
REN2
OE
D0
27
26
25
24
23
22
21
29
28
432
1
32 31 30
14 15 16 17 18 19 20
INDEX
4092 drw02a
PIN DESCRIPTIONS


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