ZN448E datasheet(4/18 Pages) ETC

Part #	ZN448E

Description	8-BIT MICROPROCESSOR COMPATIBLE A-D CONVERTER

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ZN448/9

4

After the CONVERT input goes high again the MSB decision

is made and the successive approximation routine runs to

completion.

The CONVERT pulse can be as short as 200ns; however the

MSB must be allowed to settle for at least 550ns before the

MSB decision is made. To ensure that this criterion is met

even with short CONVERT pulses the converter waits, after

the CONVERT input goes high, for a rising clock edge followed

by a falling clock edge, the MSB decision being taken on the

falling clock edge. This ensures that the MSB is allowed to

settle for at least half a clock period, or 550ns at maximum

clock frequency. The CONVERT input is not locked out during

a conversion and if it is oulsed low at any time the converter

will restart.

The

BUSY output goes high simultaneously with the LSB

decision, at the end of a conversion indicating data valid. Note

that if the three-state data outputs are enabled during a

conversion the valid data will be available at the outputs after

the rising edge of the

BUSY signal. If, however the outputs are

not enabled until after

BUSY goes high then the data will be

subject to the propagation delay of the three-state buffers.

(See under DATA OUTPUTS).

Fig.3 ZN448/9 timing diagram

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