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CR16MNS944VC Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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CR16MNS944VC Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 99 page  www.national.com 6 3.5 INTERRUPTS The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and generates interrupts to the CPU. An interrupt is an event that temporarily stops the normal flow of program execution and causes a separate in- terrupt service routine to be executed. After the interrupt is serviced, CPU execution continues with the next instruction in the program following the point of interruption. Interrupts from the timers, USARTs, MICROWIRE/SPI inter- face, multi-input wake-up, and A/D converter are all maskable interrupts; they can be enabled or disabled by the software. There are 16 of these maskable interrupts, orga- nized into 16 predetermined levels of priority. The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is generated by a signal received on the NMI in- put pin. This interrupt is not available in the 44-pin packages. 3.6 MULTI-INPUT WAKE-UP The Multi-Input Wake-up (MIWU) module can be used for ei- ther of two purposes: to provide inputs for waking up (exiting) from the HALT, IDLE, or Power Save mode; or to provide general-purpose edge-triggered maskable interrupts from external sources. This eight-channel module generates one combined interrupt to the CPU based on the signals received on its eight input channels. Channels can be individually en- abled or disabled, and programmed to respond to positive or negative edges. 3.7 DUAL CLOCK AND RESET The Dual Clock and Reset (CLK2RES) module generates a high-speed main system clock from an external crystal net- work. It also provides the main system reset signal and a power-on reset function. In the 80-pin package, the module also generates a slow sys- tem clock (32.768 KHz) from another external crystal net- work. The slow clock is used for operating the device in power-save mode. For the 44-pin devices and for devices not using a secondary crystal network, the slow clock can be generated by dividing the high-speed main clock by a pres- caler factor. 3.8 POWER MANAGEMENT The Power Management Module (PMM) improves the effi- ciency of the device by changing the operating mode (and therefore the power consumption) according to the current level of activity. The device can operate in any of four power modes: • Active: The device operates at full speed using the high- frequency clock. All device functions are fully operational. • Power Save: The device operates at reduced speed using the slow clock. The CPU and some modules can continue to operate at this low speed. • IDLE: The device is inactive except for the Power Man- agement Module and Timing and Watchdog Module, which continue to operate using the slow clock. • HALT: The device is inactive but still retains its internal state (RAM and register contents). 3.9 MULTI-FUNCTION TIMER The Multi-Function Timer (MFT16) module contains two inde- pendent timer/counter units called MFT1 and MFT2, each containing a pair of 16-bit timer/counter registers. Each timer/ counter unit can be configured to operate in any of the follow- ing modes: • Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a specified width and duty cycle, and which also provides a general-purpose timer/counter • Dual Input Capture mode, which measures the elapsed time between occurrences of external events, and which also provides a general-purpose timer/counter • Dual Independent Timer mode, which generates system timing signals or counts occurrences of external events • Single Input Capture and Single Timer mode, which pro- vides one external event counter and one system timer 3.10 REAL-TIME TIMER AND WATCHDOG The Timing and Watchdog Module (TWM) generates the clocks and interrupts used for timing periodic functions in the system. It also provides Watchdog protection against soft- ware errors. The module operates on the slow (32.768 KHz) clock. The real-time timer generates a periodic interrupt to the CPU at a software-programmed interval. This can be used for real- time functions such as a time-of-day clock. The Watchdog is designed to detect program execution er- rors such as an infinite loop or a “runaway” program. Once Watchdog operation is initiated, the application program must periodically write a specific value to a Watchdog regis- ter, within specific time intervals. If the software fails to do so, a Watchdog error is triggered, which resets the device. 3.11 USART The USART is a Universal Synchronous/Asynchronous Re- ceiver-Transmitter, a device used for serial communications. It supports a wide range of programmable baud rates and data formats, and handles parity generation and several er- ror detection schemes. The baud rate is generated on-chip, under software control. The synchronous mode of operation is not available in the 44-pin devices. 3.12 MICROWIRE/SPI The MICROWIRE/SPI (MWSPI) interface module supports asynchronous serial communications with other devices that conform to MICROWIRE or Serial Peripheral Interface (SPI) specifications. The MICROWIRE interface allows several devices to com- municate over a single system consisting of three wires: se- rial in, serial out, and shift clock. At any given time, one device on the MICROWIRE interface operates as the master, while all other devices operate as slaves. An 80-pin device supports the full set of slave select and Ready lines for multi- slave implementation, while a 44-pin device has only the ba- sic Data-in/Data-out/Clock lines, limiting its implementation to master mode. |
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